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| author | Zack Weinberg <zackw@panix.com> | 2017-05-11 20:36:15 -0400 |
|---|---|---|
| committer | Zack Weinberg <zackw@panix.com> | 2017-05-20 08:12:11 -0400 |
| commit | 81cb7a0b2b6b905a504b8b56fe3c1634adf8fb71 (patch) | |
| tree | ed0a4b6153ee727aca95aadfb8b9061cd873ca7e /sysdeps/arm/submul_1.S | |
| parent | 42a844c6a213f9219a4baa013c7305679d5dcaaa (diff) | |
| download | glibc-81cb7a0b2b6b905a504b8b56fe3c1634adf8fb71.zip glibc-81cb7a0b2b6b905a504b8b56fe3c1634adf8fb71.tar.gz glibc-81cb7a0b2b6b905a504b8b56fe3c1634adf8fb71.tar.bz2 | |
Remove sfi_* annotations from ARM assembly files.
This semi-mechanical patch removes all uses and definitions of the
sfi_breg, sfi_pld, and sfi_sp macros from various ARM-specific
assembly files. These were only used by NaCl.
* sysdeps/arm/sysdep.h
(ARM_SFI_MACROS, sfi_breg, sfi_pld, sfi_sp): Delete definitions.
* sysdeps/arm/__longjmp.S, sysdeps/arm/add_n.S
* sysdeps/arm/addmul_1.S, sysdeps/arm/arm-mcount.S
* sysdeps/arm/armv6/rawmemchr.S, sysdeps/arm/armv6/strchr.S
* sysdeps/arm/armv6/strcpy.S, sysdeps/arm/armv6/strlen.S
* sysdeps/arm/armv6/strrchr.S, sysdeps/arm/armv6t2/memchr.S
* sysdeps/arm/armv6t2/strlen.S
* sysdeps/arm/armv7/multiarch/memcpy_impl.S
* sysdeps/arm/armv7/strcmp.S, sysdeps/arm/dl-tlsdesc.S
* sysdeps/arm/memcpy.S, sysdeps/arm/memmove.S
* sysdeps/arm/memset.S, sysdeps/arm/setjmp.S
* sysdeps/arm/strlen.S, sysdeps/arm/submul_1.S:
Remove all uses of sfi_breg, sfi_pld, and sfi_sp.
Diffstat (limited to 'sysdeps/arm/submul_1.S')
| -rw-r--r-- | sysdeps/arm/submul_1.S | 18 |
1 files changed, 6 insertions, 12 deletions
diff --git a/sysdeps/arm/submul_1.S b/sysdeps/arm/submul_1.S index 34606dd..24d39d9 100644 --- a/sysdeps/arm/submul_1.S +++ b/sysdeps/arm/submul_1.S @@ -37,24 +37,19 @@ ENTRY (__mpn_submul_1) cfi_rel_offset (r6, 8) cfi_rel_offset (r7, 12) - sfi_breg r1, \ - ldr r6, [\B], #4 - sfi_breg r0, \ - ldr r7, [\B] + ldr r6, [r1], #4 + ldr r7, [r0] mov r4, #0 /* init carry in */ b 1f 0: - sfi_breg r1, \ - ldr r6, [\B], #4 /* load next ul */ + ldr r6, [r1], #4 /* load next ul */ adds r5, r5, r4 /* (lpl, c) = lpl + cl */ adc r4, ip, #0 /* cl = hpl + c */ subs r5, r7, r5 /* (lpl, !c) = rl - lpl */ - sfi_breg r0, \ - ldr r7, [\B, #4] /* load next rl */ + ldr r7, [r0, #4] /* load next rl */ it cc addcc r4, r4, #1 /* cl += !c */ - sfi_breg r0, \ - str r5, [\B], #4 + str r5, [r0], #4 1: umull r5, ip, r6, r3 /* (hpl, lpl) = ul * vl */ subs r2, r2, #1 @@ -63,8 +58,7 @@ ENTRY (__mpn_submul_1) adds r5, r5, r4 /* (lpl, c) = lpl + cl */ adc r4, ip, #0 /* cl = hpl + c */ subs r5, r7, r5 /* (lpl, !c) = rl - lpl */ - sfi_breg r0, \ - str r5, [\B], #4 + str r5, [r0], #4 it cc addcc r4, r4, #1 /* cl += !c */ mov r0, r4 /* return carry */ |