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author | Wilco <wdijkstr@arm.com> | 2014-06-02 12:20:17 +0100 |
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committer | Marcus Shawcroft <marcus.shawcroft@arm.com> | 2014-06-02 12:36:34 +0100 |
commit | c95b3011018893fcc473279768a67a24a73bbef2 (patch) | |
tree | 1f1bb0d68007030ff5bb22a54d62ff621e0abd7a /sysdeps/aarch64 | |
parent | 6b4d7a909ffeb49a7b91ba5d0bac5b4f9c5b6d1b (diff) | |
download | glibc-c95b3011018893fcc473279768a67a24a73bbef2.zip glibc-c95b3011018893fcc473279768a67a24a73bbef2.tar.gz glibc-c95b3011018893fcc473279768a67a24a73bbef2.tar.bz2 |
[AArch64] Rewrite feupdateenv (BZ 17009).
Diffstat (limited to 'sysdeps/aarch64')
-rw-r--r-- | sysdeps/aarch64/fpu/feupdateenv.c | 59 |
1 files changed, 54 insertions, 5 deletions
diff --git a/sysdeps/aarch64/fpu/feupdateenv.c b/sysdeps/aarch64/fpu/feupdateenv.c index 6d64a9b..ac2f6fe 100644 --- a/sysdeps/aarch64/fpu/feupdateenv.c +++ b/sysdeps/aarch64/fpu/feupdateenv.c @@ -22,16 +22,65 @@ int feupdateenv (const fenv_t *envp) { + fpu_control_t fpcr; + fpu_control_t fpcr_new; + fpu_control_t updated_fpcr; fpu_fpsr_t fpsr; + fpu_fpsr_t fpsr_new; + int excepts; - /* Get the current exception state. */ + _FPU_GETCW (fpcr); _FPU_GETFPSR (fpsr); + excepts = fpsr & FE_ALL_EXCEPT; - /* Install new environment. */ - fesetenv (envp); + if ((envp != FE_DFL_ENV) && (envp != FE_NOMASK_ENV)) + { + fpcr_new = envp->__fpcr; + fpsr_new = envp->__fpsr | excepts; - /* Raise the saved exceptions. */ - feraiseexcept (fpsr & FE_ALL_EXCEPT); + if (fpcr != fpcr_new) + _FPU_SETCW (fpcr_new); + + if (fpsr != fpsr_new) + _FPU_SETFPSR (fpsr_new); + + if (excepts & (fpcr_new >> FE_EXCEPT_SHIFT)) + return feraiseexcept (excepts); + + return 0; + } + + fpcr_new = fpcr & _FPU_RESERVED; + fpsr_new = fpsr & (_FPU_FPSR_RESERVED | FE_ALL_EXCEPT); + + if (envp == FE_DFL_ENV) + { + fpcr_new |= _FPU_DEFAULT; + fpsr_new |= _FPU_FPSR_DEFAULT; + } + else + { + fpcr_new |= _FPU_FPCR_IEEE; + fpsr_new |= _FPU_FPSR_IEEE; + } + + _FPU_SETFPSR (fpsr_new); + + if (fpcr != fpcr_new) + { + _FPU_SETCW (fpcr_new); + + /* Trapping exceptions are optional in AArch64; the relevant enable + bits in FPCR are RES0 hence the absence of support can be detected + by reading back the FPCR and comparing with the required value. */ + _FPU_GETCW (updated_fpcr); + + if (fpcr_new & ~updated_fpcr) + return 1; + } + + if (excepts & (fpcr_new >> FE_EXCEPT_SHIFT)) + return feraiseexcept (excepts); return 0; } |