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authorNaohiro Tamura <naohirot@jp.fujitsu.com>2021-05-27 07:44:12 +0000
committerSzabolcs Nagy <szabolcs.nagy@arm.com>2021-05-27 09:47:53 +0100
commit4f26956d5ba394eb3ade6c1c20b5c16864a00766 (patch)
tree8857e5f8fceb8555922d2fde86a38e8b6b486f4e /sysdeps/aarch64/multiarch/Makefile
parentfa527f345cbbe852ec085932fbea979956c195b5 (diff)
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aarch64: Added optimized memset for A64FX
This patch optimizes the performance of memset for A64FX [1] which implements ARMv8-A SVE and has L1 64KB cache per core and L2 8MB cache per NUMA node. The performance optimization makes use of Scalable Vector Register with several techniques such as loop unrolling, memory access alignment, cache zero fill and prefetch. SVE assembler code for memset is implemented as Vector Length Agnostic code so theoretically it can be run on any SOC which supports ARMv8-A SVE standard. We confirmed that all testcases have been passed by running 'make check' and 'make xcheck' not only on A64FX but also on ThunderX2. And also we confirmed that the SVE 512 bit vector register performance is roughly 4 times better than Advanced SIMD 128 bit register and 8 times better than scalar 64 bit register by running 'make bench'. [1] https://github.com/fujitsu/A64FX Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com> Reviewed-by: Szabolcs Nagy <Szabolcs.Nagy@arm.com>
Diffstat (limited to 'sysdeps/aarch64/multiarch/Makefile')
-rw-r--r--sysdeps/aarch64/multiarch/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/sysdeps/aarch64/multiarch/Makefile b/sysdeps/aarch64/multiarch/Makefile
index 04c3f17..7500cf1 100644
--- a/sysdeps/aarch64/multiarch/Makefile
+++ b/sysdeps/aarch64/multiarch/Makefile
@@ -2,6 +2,7 @@ ifeq ($(subdir),string)
sysdep_routines += memcpy_generic memcpy_advsimd memcpy_thunderx memcpy_thunderx2 \
memcpy_falkor memcpy_a64fx \
memset_generic memset_falkor memset_emag memset_kunpeng \
+ memset_a64fx \
memchr_generic memchr_nosimd \
strlen_mte strlen_asimd
endif