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| author | H.J. Lu <hjl.tools@gmail.com> | 2015-03-31 13:17:51 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2015-03-31 13:18:10 -0700 |
| commit | a3d9ab5070b56b49aa91be2887fa5b118012b2cd (patch) | |
| tree | 4352143efb08c51ec9cb480489e847de724afb06 /NEWS | |
| parent | 83569fb894050db7430047da2219ca50c68f882a (diff) | |
| download | glibc-a3d9ab5070b56b49aa91be2887fa5b118012b2cd.zip glibc-a3d9ab5070b56b49aa91be2887fa5b118012b2cd.tar.gz glibc-a3d9ab5070b56b49aa91be2887fa5b118012b2cd.tar.bz2 | |
Limit threads sharing L2 cache to 2 for SLM/KNL
Silvermont and Knights Landing have a modular system design with two cores
sharing an L2 cache. If more than 2 cores are detected to shared L2 cache,
it should be adjusted for Silvermont and Knights Landing.
[BZ #18185]
* sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Limit threads
sharing L2 cache to 2 for Silvermont/Knights Landing.
Diffstat (limited to 'NEWS')
| -rw-r--r-- | NEWS | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -15,7 +15,7 @@ Version 2.22 17932, 17944, 17949, 17964, 17965, 17967, 17969, 17978, 17987, 17991, 17996, 17998, 17999, 18019, 18020, 18029, 18030, 18032, 18036, 18038, 18039, 18042, 18043, 18046, 18047, 18068, 18080, 18093, 18100, 18104, - 18110, 18111, 18128, 18138. + 18110, 18111, 18128, 18138, 18185. * A powerpc and powerpc64 optimization for TLS, similar to TLS descriptors for LD and GD on x86 and x86-64, has been implemented. You will need |