blob: 1ca14135bbc4112b13f01df542fccb2da951e4e3 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
|
/* Sparc target configuration file. -*- C -*- */
#ifndef SPARC_TCONFIG_H
#define SPARC_TCONFIG_H
/* See sim-hload.c. We properly handle LMA. */
#define SIM_HANDLES_LMA 1
/* Device support. FIXME: revisit. */
#define WITH_DEVICES 1
/* This is a global setting. Different cpu families can't mix-n-match -scache
and -pbb. However some cpu families may use -simple while others use
one of -scache/-pbb. */
#define WITH_SCACHE_PBB 0
/* Simple-engine branch support.
Delay slots, annuling, and traps are (currently) handled by using the
simple engine and doing all the work in SEM_{,N}BRANCH_FINI. */
#define TARGET_SEM_BRANCH_FINI(vpc, bool_attrs, taken_p) \
do { \
IADDR npc = GET_H_NPC (); \
if (CGEN_BOOL_ATTR ((bool_attrs), CGEN_INSN_DELAY_SLOT) && taken_p) \
{ \
SET_H_PC (npc); \
SET_H_NPC (vpc); \
} \
else if (CGEN_BOOL_ATTR ((bool_attrs), CGEN_INSN_TRAP) && taken_p) \
{ \
SET_H_PC (vpc); \
SET_H_NPC ((vpc) + 4); \
} \
else \
{ \
SET_H_PC (npc); \
SET_H_NPC (npc + 4); \
} \
} while (0)
#define TARGET_SEM_NBRANCH_FINI(vpc, bool_attrs) \
do { \
IADDR npc = GET_H_NPC (); \
SET_H_PC (npc); \
SET_H_NPC (npc + 4); \
} while (0)
#endif /* SPARC_TCONFIG_H */
|
