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Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
* config.in: Ditto.
Tue Aug 26 10:41:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (sim_kill): Delete.
(sim_create_inferior): Add ABFD argument.
(sim_load): Move setting of PC from here.
(sim_create_inferior): To here.
Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
* config.in: Ditto.
Mon Aug 25 16:14:44 1997 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (sim_open): Add ABFD argument.
Tue Jun 24 13:46:20 1997 Jeffrey A Law (law@cygnus.com)
* interp.c (sim_resume): Clear State.exited.
(sim_stop_reason): If State.exited is nonzero, then indicate that
the simulator exited instead of stopped.
* mn10300_sim.h (struct _state): Add exited field.
* simops.c (syscall): Set State.exited for SYS_exit.
Wed Jun 11 22:07:56 1997 Jeffrey A Law (law@cygnus.com)
* simops.c: Fix thinko in last change.
Tue Jun 10 12:31:32 1997 Jeffrey A Law (law@cygnus.com)
* simops.c: "call" stores the callee saved registers into the
stack! Update the stack pointer properly when done with
register saves.
* simops.c: Fix return address computation for "call" instructions.
Thu May 22 01:43:11 1997 Jeffrey A Law (law@cygnus.com)
* interp.c (sim_open): Fix typo.
Wed May 21 23:27:58 1997 Jeffrey A Law (law@cygnus.com)
* interp.c (sim_resume): Add missing case in big switch
statement (for extb instruction).
Tue May 20 17:51:30 1997 Jeffrey A Law (law@cygnus.com)
* interp.c: Replace all references to load_mem and store_mem
with references to load_byte, load_half, load_3_byte, load_word
and store_byte, store_half, store_3_byte, store_word.
(INLINE): Delete definition.
(load_mem_big): Likewise.
(max_mem): Make it global.
(dispatch): Make this function inline.
(load_mem, store_mem): Delete functions.
* mn10300_sim.h (INLINE): Define.
(RLW): Delete unused definition.
(load_mem, store_mem): Delete declarations.
(load_mem_big): New definition.
(load_byte, load_half, load_3_byte, load_word): New functions.
(store_byte, store_half, store_3_byte, store_word): New functions.
* simops.c: Replace all references to load_mem and store_mem
with references to load_byte, load_half, load_3_byte, load_word
and store_byte, store_half, store_3_byte, store_word.
Tue May 20 10:21:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (sim_open): Add callback to arguments.
(sim_set_callbacks): Delete SIM_DESC argument.
Mon May 19 13:54:22 1997 Jeffrey A Law (law@cygnus.com)
* interp.c (dispatch): Make this an inline function.
* simops.c (syscall): Use callback->write regardless of
what file descriptor we're writing too.
Sun May 18 16:46:31 1997 Jeffrey A Law (law@cygnus.com)
* interp.c (load_mem_big): Remove function. It's now a macro
defined elsewhere.
(compare_simops): New function.
(sim_open): Sort the Simops table before inserting entries
into the hash table.
* mn10300_sim.h: Remove unused #defines.
(load_mem_big): Define.
Fri May 16 16:36:17 1997 Jeffrey A Law (law@cygnus.com)
* interp.c (load_mem): If we get a load from an out of range
address, abort.
(store_mem): Likewise for stores.
(max_mem): New variable.
Tue May 6 13:24:36 1997 Jeffrey A Law (law@cygnus.com)
* mn10300_sim.h: Fix ordering of bits in the PSW.
* interp.c: Improve hashing routine to avoid long list
traversals for common instructions. Add HASH_STAT support.
Rewrite opcode dispatch code using a big switch instead of
cascaded if/else statements. Avoid useless calls to load_mem.
Mon May 5 18:07:48 1997 Jeffrey A Law (law@cygnus.com)
* mn10300_sim.h (struct _state): Add space for mdrq register.
(REG_MDRQ): Define.
* simops.c: Don't abort for trap. Add support for the extended
instructions, "getx", "putx", "mulq", "mulqu", "sat16", "sat24",
and "bsch".
Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Fri Apr 18 14:04:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (sim_stop): Add stub function.
Thu Apr 17 03:26:59 1997 Doug Evans <dje@canuck.cygnus.com>
* Makefile.in (SIM_OBJS): Add sim-load.o.
* interp.c (sim_kind, myname): New static locals.
(sim_open): Set sim_kind, myname. Ignore -E arg.
(sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
load file into simulator. Set start address from bfd.
(sim_create_inferior): Return SIM_RC. Delete arg start_address.
Wed Apr 16 19:30:44 1997 Andrew Cagney <cagney@b1.cygnus.com>
* simops.c (OP_F020): SYS_execv, SYS_time, SYS_times, SYS_utime
only include if implemented by host.
(OP_F020): Typecast arg passed to time function;
Mon Apr 7 23:57:49 1997 Jeffrey A Law (law@cygnus.com)
* simops.c (syscall): Handle new mn10300 calling conventions.
Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
* config.in: Ditto.
Fri Apr 4 20:02:37 1997 Ian Lance Taylor <ian@cygnus.com>
* Makefile.in: Change mn10300-opc.o to m10300-opc.o, to match
corresponding change in opcodes directory.
Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
* interp.c (sim_open): New arg `kind'.
* configure: Regenerated to track ../common/aclocal.m4 changes.
Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Thu Mar 20 11:58:02 1997 Jeffrey A Law (law@cygnus.com)
* simops.c: Fix register extraction for a two "movbu" variants.
Somewhat simplify "sub" instructions.
Correctly sign extend operands for "mul". Put the correct
half of the result in MDR for "mul" and "mulu".
Implement remaining instructions.
Tweak opcode for "syscall".
Tue Mar 18 14:21:21 1997 Jeffrey A Law (law@cygnus.com)
* simops.c: Do syscall emulation in "syscall" instruction. Add
dummy "trap" instruction.
Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
* configure: Re-generate.
Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
* configure: Regenerate to track ../common/aclocal.m4 changes.
Thu Mar 13 12:54:45 1997 Doug Evans <dje@canuck.cygnus.com>
* interp.c (sim_open): New SIM_DESC result. Argument is now
in argv form.
(other sim_*): New SIM_DESC argument.
Wed Mar 12 15:04:00 1997 Jeffrey A Law (law@cygnus.com)
* simops.c: Fix carry bit computation for "add" instructions.
* simops.c: Fix typos in bset insns. Fix arguments to store_mem
for bset imm8,(d8,an) and bclr imm8,(d8,an).
Wed Mar 5 15:00:10 1997 Jeffrey A Law (law@cygnus.com)
* simops.c: Fix register references when computing Z and N bits
for lsr imm8,dn.
Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
* Makefile.in (@COMMON_MAKEFILE_FRAG): Use
COMMON_{PRE,POST}_CONFIG_FRAG instead.
* configure.in: sinclude ../common/aclocal.m4.
* configure: Regenerated.
Fri Jan 24 10:47:25 1997 Jeffrey A Law (law@cygnus.com)
* interp.c (init_system): Allocate 2^19 bytes of space for the
simulator.
Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
* configure configure.in Makefile.in: Update to new configure
scheme which is more compatible with WinGDB builds.
* configure.in: Improve comment on how to run autoconf.
* configure: Re-run autoconf to get new ../common/aclocal.m4.
* Makefile.in: Use autoconf substitution to install common
makefile fragment.
Tue Jan 21 15:03:04 1997 Jeffrey A Law (law@cygnus.com)
* simops.c: Undo last change to "rol" and "ror", original code
was correct!
Thu Jan 16 11:28:14 1997 Jeffrey A Law (law@cygnus.com)
* simops.c: Fix "rol" and "ror".
Wed Jan 15 06:45:58 1997 Jeffrey A Law (law@cygnus.com)
* simops.c: Fix typo in last change.
Mon Jan 13 13:22:35 1997 Jeffrey A Law (law@cygnus.com)
* simops.c: Use REG macros in few places not using them yet.
Mon Jan 6 16:21:19 1997 Jeffrey A Law (law@cygnus.com)
* mn10300_sim.h (struct _state): Fix number of registers!
Tue Dec 31 16:20:41 1996 Jeffrey A Law (law@cygnus.com)
* mn10300_sim.h (struct _state): Put all registers into a single
array to make gdb implementation easier.
(REG_*): Add definitions for all registers in the state array.
(SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
* simops.c: Related changes.
Wed Dec 18 10:10:45 1996 Jeffrey A Law (law@cygnus.com)
* interp.c (sim_resume): Handle 0xff as a single byte insn.
* simops.c: Fix overflow computation for "add" and "inc"
instructions.
Mon Dec 16 10:03:52 1996 Jeffrey A Law (law@cygnus.com)
* simops.c: Handle "break" instruction.
* simops.c: Fix restoring the PC for "ret" and "retf" instructions.
Wed Dec 11 09:53:10 1996 Jeffrey A Law (law@cygnus.com)
* gencode.c (write_opcodes): Also write out the format of the
opcode.
* mn10300_sim.h (simops): Add "format" field.
* interp.c (sim_resume): Deal with endianness issues here.
Tue Dec 10 15:05:37 1996 Jeffrey A Law (law@cygnus.com)
* simops.c (REG0_4): Define.
Use REG0_4 for indexed loads/stores.
Sat Dec 7 09:50:28 1996 Jeffrey A Law (law@cygnus.com)
* simops.c (REG0_16): Fix typo.
Fri Dec 6 14:13:34 1996 Jeffrey A Law (law@cygnus.com)
* simops.c: Call abort for any instruction that's not currently
simulated.
* simops.c: Define accessor macros to extract register
values from instructions. Use them consistently.
* interp.c: Delete unused global variable "OP".
(sim_resume): Remove unused variable "opcode".
* simops.c: Fix some uninitialized variable problems, add
parens to fix various -Wall warnings.
* gencode.c (write_header): Add "insn" and "extension" arguments
to the OP_* declarations.
(write_template): Similarly for function templates.
* interp.c (insn, extension): Remove global variables. Instead
pass them as arguments to the OP_* functions.
* mn10300_sim.h: Remove decls for "insn" and "extension".
* simops.c (OP_*): Accept "insn" and "extension" as arguments
instead of using globals.
Thu Dec 5 22:26:31 1996 Jeffrey A Law (law@cygnus.com)
* simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
* simops.c: Fix thinkos in last change to "inc dn".
Wed Dec 4 10:57:53 1996 Jeffrey A Law (law@cygnus.com)
* simops.c: "add imm,sp" does not effect the condition codes.
"inc dn" does effect the condition codes.
Tue Dec 3 17:37:45 1996 Jeffrey A Law (law@cygnus.com)
* simops.c: Treat both operands as signed values for
"div" instruction.
* simops.c: Fix simulation of division instructions.
Fix typos/thinkos in several "cmp" and "sub" instructions.
Mon Dec 2 12:31:40 1996 Jeffrey A Law (law@cygnus.com)
* simops.c: Fix carry bit handling in "sub" and "cmp"
instructions.
* simops.c: Fix "mov imm8,an" and "mov imm16,dn".
Sun Dec 1 16:05:42 1996 Jeffrey A Law (law@cygnus.com)
* simops.c: Fix overflow computation for many instructions.
* simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
* simops.c: Fix "mov am, dn".
* simops.c: Fix more bugs in "add imm,an" and
"add imm,dn".
Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com)
* simops.c: Fix bugs in "movm" and "add imm,an".
* simops.c: Don't lose the upper 24 bits of the return
pointer in "call" and "calls" instructions. Rough cut
at emulated system calls.
* simops.c: Implement the remaining 5, 6 and 7 byte instructions.
* simops.c: Implement remaining 4 byte instructions.
* simops.c: Implement remaining 3 byte instructions.
* simops.c: Implement remaining 2 byte instructions. Call
abort for instructions we're not implementing now.
Tue Nov 26 15:43:41 1996 Jeffrey A Law (law@cygnus.com)
* simops.c: Implement lots of random instructions.
* simops.c: Implement "movm" and "bCC" insns.
* mn10300_sim.h (_state): Add another register (MDR).
(REG_MDR): Define.
* simops.c: Implement "cmp", "calls", "rets", "jmp" and
a few additional random insns.
* mn10300_sim.h (PSW_*): Define for CC status tracking.
(REG_D0, REG_A0, REG_SP): Define.
* simops.c: Implement "add", "addc" and a few other random
instructions.
* gencode.c, interp.c: Snapshot current simulator code.
Mon Nov 25 12:46:38 1996 Jeffrey A Law (law@cygnus.com)
* Makefile.in, config.in, configure, configure.in: New files.
* gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
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