aboutsummaryrefslogtreecommitdiff
path: root/sim/aarch64/decode.h
blob: 416aca428d3d5e40dc8a52c5ae1bf6144cddeae1 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
/* decode.h -- Prototypes for AArch64 simulator decoder functions.

   Copyright (C) 2015-2022 Free Software Foundation, Inc.

   Contributed by Red Hat.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef _DECODE_H
#define _DECODE_H

#include <sys/types.h>
#include "cpustate.h"

/* Codes used in conditional instructions

   These are passed to conditional operations to identify which
   condition to test for.  */

typedef enum CondCode
{
  EQ = 0x0, /* meaning Z == 1 */
  NE = 0x1, /* meaning Z == 0 */
  HS = 0x2, /* meaning C == 1 */
  CS = HS,
  LO = 0x3, /* meaning C == 0 */
  CC = LO,
  MI = 0x4, /* meaning N == 1 */
  PL = 0x5, /* meaning N == 0 */
  VS = 0x6, /* meaning V == 1 */
  VC = 0x7, /* meaning V == 0 */
  HI = 0x8, /* meaning C == 1 && Z == 0 */
  LS = 0x9, /* meaning !(C == 1 && Z == 0) */
  GE = 0xa, /* meaning N == V */
  LT = 0xb, /* meaning N != V */
  GT = 0xc, /* meaning Z == 0 && N == V */
  LE = 0xd, /* meaning !(Z == 0 && N == V) */
  AL = 0xe, /* meaning ANY */
  NV = 0xf  /* ditto */
} CondCode;

/* Certain addressing modes for load require pre or post writeback of
   the computed address to a base register.  */

typedef enum WriteBack
{
  Post = 0,
  Pre = 1,
  NoWriteBack = -1
} WriteBack;

/* Certain addressing modes for load require an offset to
   be optionally scaled so the decode needs to pass that
   through to the execute routine.  */

typedef enum Scaling
{
  Unscaled = 0,
  Scaled = 1,
  NoScaling = -1
} Scaling;

/* When we do have to scale we do so by shifting using
   log(bytes in data element - 1) as the shift count.
   so we don't have to scale offsets when loading
   bytes.  */

typedef enum ScaleShift
{
  ScaleShift16 = 1,
  ScaleShift32 = 2,
  ScaleShift64 = 3,
  ScaleShift128 = 4
} ScaleShift;

/* One of the addressing modes for load requires a 32-bit register
   value to be either zero- or sign-extended for these instructions
   UXTW or SXTW should be passed.

   Arithmetic register data processing operations can optionally
   extend a portion of the second register value for these
   instructions the value supplied must identify the portion of the
   register which is to be zero- or sign-exended.  */

typedef enum Extension
{
  UXTB = 0,
  UXTH = 1,
  UXTW = 2,
  UXTX = 3,
  SXTB = 4,
  SXTH = 5,
  SXTW = 6,
  SXTX = 7,
  NoExtension = -1
} Extension;

/* Arithmetic and logical register data processing operations
   optionally perform a shift on the second register value.  */

typedef enum Shift
{
  LSL = 0,
  LSR = 1,
  ASR = 2,
  ROR = 3
} Shift;

/* Bit twiddling helpers for instruction decode.  */

/* 32 bit mask with bits [hi,...,lo] set.  */
static inline uint32_t
mask32 (int hi, int lo)
{
  int nbits = (hi + 1) - lo;
  return ((1 << nbits) - 1) << lo;
}

/* 64 bit mask with bits [hi,...,lo] set.  */
static inline uint64_t
mask64 (int hi, int lo)
{
  int nbits = (hi + 1) - lo;
  return ((1L << nbits) - 1) << lo;
}

/* Pick bits [hi,...,lo] from val.  */
static inline uint32_t
pick32 (uint32_t val, int hi, int lo)
{
  return val & mask32 (hi, lo);
}

/* Pick bits [hi,...,lo] from val.  */
static inline uint64_t
pick64 (uint64_t val, int hi, int lo)
{
  return val & mask64 (hi, lo);
}

/* Pick bits [hi,...,lo] from val and shift to [(hi-(newlo - lo)),newlo].  */
static inline uint32_t
pickshift32 (uint32_t val, int hi, int lo, int newlo)
{
  uint32_t bits = pick32 (val, hi, lo);

  if (lo < newlo)
    return bits << (newlo - lo);

  return bits >> (lo - newlo);
}

/* Mask [hi,lo] and shift down to start at bit 0.  */
static inline uint32_t
pickbits32 (uint32_t val, int hi, int lo)
{
  return pick32 (val, hi, lo) >> lo;
}

/* Mask [hi,lo] and shift down to start at bit 0.  */
static inline uint64_t
pickbits64 (uint64_t val, int hi, int lo)
{
  return pick64 (val, hi, lo) >> lo;
}

static inline uint32_t
uimm (uint32_t val, int hi, int lo)
{
  return pickbits32 (val, hi, lo);
}

static inline int32_t
simm32 (uint32_t val, int hi, int lo)
{
  union
  {
    uint32_t u;
    int32_t n;
  } x;

  x.u = val << (31 - hi);
  return x.n >> (31 - hi + lo);
}

static inline int64_t
simm64 (uint64_t val, int hi, int lo)
{
  union
  {
    uint64_t u;
    int64_t n;
  } x;

  x.u = val << (63 - hi);
  return x.n >> (63 - hi + lo);
}

/* Operation decode.
   Bits [28,24] are the primary dispatch vector.  */

static inline uint32_t
dispatchGroup (uint32_t val)
{
  return pickshift32 (val, 28, 25, 0);
}

/* The 16 possible values for bits [28,25] identified by tags which
   map them to the 5 main instruction groups LDST, DPREG, ADVSIMD,
   BREXSYS and DPIMM.

   An extra group PSEUDO is included in one of the unallocated ranges
   for simulator-specific pseudo-instructions.  */

enum DispatchGroup
{
  GROUP_PSEUDO_0000,
  GROUP_UNALLOC_0001,
  GROUP_UNALLOC_0010,
  GROUP_UNALLOC_0011,
  GROUP_LDST_0100,
  GROUP_DPREG_0101,
  GROUP_LDST_0110,
  GROUP_ADVSIMD_0111,
  GROUP_DPIMM_1000,
  GROUP_DPIMM_1001,
  GROUP_BREXSYS_1010,
  GROUP_BREXSYS_1011,
  GROUP_LDST_1100,
  GROUP_DPREG_1101,
  GROUP_LDST_1110,
  GROUP_ADVSIMD_1111
};

/* Bits [31, 29] of a Pseudo are the secondary dispatch vector.  */

static inline uint32_t
dispatchPseudo (uint32_t val)
{
  return pickshift32 (val, 31, 29, 0);
}

/* The 8 possible values for bits [31,29] in a Pseudo Instruction.
   Bits [28,25] are always 0000.  */

enum DispatchPseudo
{
  PSEUDO_UNALLOC_000, /* Unallocated.  */
  PSEUDO_UNALLOC_001, /* Ditto.  */
  PSEUDO_UNALLOC_010, /* Ditto.  */
  PSEUDO_UNALLOC_011, /* Ditto.  */
  PSEUDO_UNALLOC_100, /* Ditto.  */
  PSEUDO_UNALLOC_101, /* Ditto.  */
  PSEUDO_CALLOUT_110, /* CALLOUT -- bits [24,0] identify call/ret sig.  */
  PSEUDO_HALT_111     /* HALT -- bits [24, 0] identify halt code.  */
};

/* Bits [25, 23] of a DPImm are the secondary dispatch vector.  */

static inline uint32_t
dispatchDPImm (uint32_t instr)
{
  return pickshift32 (instr, 25, 23, 0);
}

/* The 8 possible values for bits [25,23] in a Data Processing Immediate
   Instruction. Bits [28,25] are always 100_.  */

enum DispatchDPImm
{
  DPIMM_PCADR_000,  /* PC-rel-addressing.  */
  DPIMM_PCADR_001,  /* Ditto.  */
  DPIMM_ADDSUB_010, /* Add/Subtract (immediate).  */
  DPIMM_ADDSUB_011, /* Ditto.  */
  DPIMM_LOG_100,    /* Logical (immediate).  */
  DPIMM_MOV_101,    /* Move Wide (immediate).  */
  DPIMM_BITF_110,   /* Bitfield.  */
  DPIMM_EXTR_111    /* Extract.  */
};

/* Bits [29,28:26] of a LS are the secondary dispatch vector.  */

static inline uint32_t
dispatchLS (uint32_t instr)
{
  return (  pickshift32 (instr, 29, 28, 1)
	  | pickshift32 (instr, 26, 26, 0));
}

/* The 8 possible values for bits [29,28:26] in a Load/Store
   Instruction. Bits [28,25] are always _1_0.  */

enum DispatchLS
{
  LS_EXCL_000,    /* Load/store exclusive (includes some unallocated).  */
  LS_ADVSIMD_001, /* AdvSIMD load/store (various -- includes some unallocated).  */
  LS_LIT_010,     /* Load register literal (includes some unallocated).  */
  LS_LIT_011,     /* Ditto.  */
  LS_PAIR_100,    /* Load/store register pair (various).  */
  LS_PAIR_101,    /* Ditto.  */
  LS_OTHER_110,   /* Other load/store formats.  */
  LS_OTHER_111    /* Ditto.  */
};

/* Bits [28:24:21] of a DPReg are the secondary dispatch vector.  */

static inline uint32_t
dispatchDPReg (uint32_t instr)
{
  return (  pickshift32 (instr, 28, 28, 2)
	  | pickshift32 (instr, 24, 24, 1)
	  | pickshift32 (instr, 21, 21, 0));
}

/* The 8 possible values for bits [28:24:21] in a Data Processing
   Register Instruction. Bits [28,25] are always _101.  */

enum DispatchDPReg
{
  DPREG_LOG_000,     /* Logical (shifted register).  */
  DPREG_LOG_001,     /* Ditto.  */
  DPREG_ADDSHF_010,  /* Add/subtract (shifted register).  */
  DPREG_ADDEXT_011,  /* Add/subtract (extended register).  */
  DPREG_ADDCOND_100, /* Add/subtract (with carry) AND
                        Cond compare/select AND
                        Data Processing (1/2 source).  */
  DPREG_UNALLOC_101, /* Unallocated.  */
  DPREG_3SRC_110,    /* Data Processing (3 source).  */
  DPREG_3SRC_111     /* Data Processing (3 source).  */
};

/* bits [31,29] of a BrExSys are the secondary dispatch vector.  */

static inline uint32_t
dispatchBrExSys (uint32_t instr)
{
  return pickbits32 (instr, 31, 29);
}

/* The 8 possible values for bits [31,29] in a Branch/Exception/System
   Instruction. Bits [28,25] are always 101_.  */

enum DispatchBr
{
  BR_IMM_000,     /* Unconditional branch (immediate).  */
  BR_IMMCMP_001,  /* Compare & branch (immediate) AND
                     Test & branch (immediate).  */
  BR_IMMCOND_010, /* Conditional branch (immediate) AND Unallocated.  */
  BR_UNALLOC_011, /* Unallocated.  */
  BR_IMM_100,     /* Unconditional branch (immediate).  */
  BR_IMMCMP_101,  /* Compare & branch (immediate) AND
                     Test & branch (immediate).  */
  BR_REG_110,     /* Unconditional branch (register) AND System AND
                     Excn gen AND Unallocated.  */
  BR_UNALLOC_111  /* Unallocated.  */
};

/* TODO still need to provide secondary decode and dispatch for
   AdvSIMD Insructions with instr[28,25] = 0111 or 1111.  */

#endif /* _DECODE_H */