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2023-12-15sim: bfin: fix typo in bf52x portsMike Frysinger1-6/+6
2023-12-15sim: warnings: enable -Wunused-but-set-variableMike Frysinger2-2/+2
2023-12-15sim: mn10300: fix incorrect implementation of a few insnsMike Frysinger1-7/+7
2023-12-14sim: m32r: fix mloop.in variant stamp depsMike Frysinger2-4/+4
2023-12-14sim: m32r: use @cpu@_fill_argbuf_tp to set trace & profile stateMike Frysinger2-16/+8
2023-12-14sim: igen: do not reindent literal semantics outputMike Frysinger1-2/+9
2023-12-10Improve performance of the H8 simulatorJeff Law1-2/+96
2023-12-07sim: aarch64: fix -Wunused-but-set-variable warningsMike Frysinger1-2/+1
2023-12-07sim: common: fix -Wunused-but-set-variable warningsMike Frysinger1-2/+0
2023-12-07sim: ppc: fix -Wunused-but-set-variable warningsMike Frysinger1-2/+0
2023-12-07sim: v850: fix -Wunused-but-set-variable warningsMike Frysinger2-11/+8
2023-12-07sim: sh: fix -Wunused-but-set-variable warningsMike Frysinger1-2/+0
2023-12-07sim: msp430: fix -Wunused-but-set-variable warningsMike Frysinger1-2/+1
2023-12-07sim: mips: fix -Wunused-but-set-variable warningsMike Frysinger1-3/+5
2023-12-07sim: mcore: fix -Wunused-but-set-variable warningsMike Frysinger1-4/+0
2023-12-07sim: m68hc11: fix -Wunused-but-set-variable warningsMike Frysinger2-6/+0
2023-12-07sim: h8300: fix -Wunused-but-set-variable warningsMike Frysinger1-8/+0
2023-12-07sim: ft32: fix -Wunused-but-set-variable warningsMike Frysinger1-4/+0
2023-12-07sim: frv: fix -Wunused-but-set-variable warningsMike Frysinger3-15/+0
2023-12-07sim: erc32: fix -Wunused-but-set-variable warningsMike Frysinger2-15/+4
2023-12-07sim: d10v: fix -Wunused-but-set-variable warningsMike Frysinger1-2/+2
2023-12-07sim: cris: fix -Wunused-but-set-variable warningsMike Frysinger3-4/+9
2023-12-07sim: bfin: fix -Wunused-but-set-variable warningsMike Frysinger7-23/+7
2023-12-07sim: bfin: gui: fix -Wunused-but-set-variable warningsMike Frysinger1-12/+22
2023-12-07sim: arm: fix -Wunused-but-set-variable warningsMike Frysinger1-2/+0
2023-12-07sim: m32r: fix syslog callMike Frysinger1-1/+2
2023-12-07sim: m32r: include more glibc headers for the funcs we use [PR sim/29752]Mike Frysinger1-0/+5
2023-12-07sim: m32r: add more cgen prototypes for trapsMike Frysinger1-0/+12
2023-12-07sim: m32r: add more cgen prototypes to enable -Werror in most filesMike Frysinger3-24/+27
2023-12-07sim: warnings: disable -Wenum-conversion fow now [PR sim/29752]Mike Frysinger2-0/+4
2023-12-06sim: support dlopen in -lcMike Frysinger2-2/+2
2023-12-06sim: cris: move generated file to right placeMike Frysinger2-14121/+1
2023-12-06sim: warnings: add more flagsMike Frysinger2-8/+37
2023-12-05sim: warnings: sync some build logic from gdbsupportMike Frysinger2-15/+65
2023-12-05sim: mips: fix sim_fpu usageMike Frysinger1-4/+4
2023-12-05sim: sh: trim trailing whitespace in generated codeMike Frysinger1-15/+15
2023-12-05sim: mn10300: fix sim_engine_halt callMike Frysinger1-1/+2
2023-12-05sim: m32c: use UTF-8 encodingMike Frysinger1-1/+1
2023-12-04sim: rx: mark unused static var as unusedMike Frysinger1-0/+1
2023-12-04sim: rx: constify some read-only global varsMike Frysinger1-3/+3
2023-12-04sim: warnings: enable only for development buildsMike Frysinger5-5/+13
2023-12-04sim: ppc: fix implicit enum conversionMike Frysinger1-3/+3
2023-12-04sim: ppc: fix -Wmisleading-indentation warningsMike Frysinger1-1/+1
2023-12-04sim: ppc: cleanup getrusage declsMike Frysinger3-17/+2
2023-12-01Fix right shifts in mcore simulator on 64 bit hosts.Jeff Law3-2/+55
2023-11-28sim: bpf: do not use semicolon to begin commentsJose E. Marchesi11-292/+292
2023-11-16sim: mips: Change E_MIPS_* to EF_MIPS_*Ying Huang1-2/+2
2023-10-18sim/riscv: fix JALR instruction simulationJaydeep Patil3-4/+32
2023-10-15sim: mips: fix printf stringMike Frysinger1-1/+1
2023-10-11[RFA] Fix for mcore simulatorJeff Law3-4/+56
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