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path: root/sim/sh/interp.c
AgeCommit message (Expand)AuthorFilesLines
2017-02-13sim: use ARRAY_SIZE instead of ad-hoc sizeof calculationsMike Frysinger1-1/+1
2016-04-10Fix primary reason why the SH simulation hasn't been working on 64 bit hosts.Oleg Endo1-34/+12
2016-04-09Adjust default memory size and stack base address for SH simulator.Oleg Endo1-3/+3
2016-01-06sim: sim_{create_inferior,open,parse_args}: constify argv/env slightlyMike Frysinger1-2/+4
2016-01-03sim: parse_args: display getopt error ourselvesMike Frysinger1-3/+1
2016-01-03sim: use libiberty countargv in more placesMike Frysinger1-17/+3
2016-01-03sim: drop host endian configure optionMike Frysinger1-1/+1
2016-01-03sim: convert to bfd_endianMike Frysinger1-2/+2
2015-12-30sim: arm/d10v/h8300/m68hc11/microblaze/mips/mn10300/moxie/sh/v850: convert to...Mike Frysinger1-4/+6
2015-11-22sim: sh: delete global callback/argvMike Frysinger1-44/+35
2015-11-15sim: sim-close: unify sim_close logicMike Frysinger1-6/+0
2015-04-17sim: arm/cr16/d10v/h8300/microblaze/sh: fill out sim-cpu pc fetch/store helpersMike Frysinger1-0/+21
2015-03-28sim: sh: convert to nrunMike Frysinger1-204/+74
2015-03-28sim: sh: clean up some warningsMike Frysinger1-209/+98
2014-03-10sim: constify arg to sim_do_commandMike Frysinger1-4/+4
2014-03-05sim: constify prog_nameMike Frysinger1-1/+1
2014-02-17sim: delete duplicate SIGINT handlingMike Frysinger1-13/+0
2014-01-07remove PARAMS from simTom Tromey1-16/+16
2013-03-15gdb:Steve Ellcey1-1/+1
2012-02-16Update sim_fetch_register, sim_store_register for sh and mn10300.Kevin Buettner1-3/+3
2011-04-16sim: add sim_complete_command stubs for non-common-using portsMike Frysinger1-0/+6
2010-04-14sim: constify sim_write source buffer (part 2)Mike Frysinger1-2/+2
2010-02-14 * interp.c: Don't include sysdep.h.Masaki Muranaka1-1/+18
2008-02-042008-02-04 Antony King <antony.king@st.com>Andrew Stubbs1-13/+8
2005-11-102005-11-10 Andrew Stubbs <andrew.stubbs@st.com>Andrew Stubbs1-1/+1
2005-09-19 * interp.c (<sys/mman.h>): Include.Joern Rennecke1-5/+35
2005-08-02 * interp.c (strswaplen): Add one for '\0' delimiter.Joern Rennecke1-1/+5
2004-09-08 * gencode.c (movua.l): Compensate for endianness.Corinna Vinschen1-27/+321
2004-02-122004-02-12 Michael Snyder <msnyder@redhat.com>Michael Snyder1-3/+3
2004-01-102004-01-07 Michael Snyder <msnyder@redhat.com>Michael Snyder1-55/+60
2004-01-092004-01-07 Michael Snyder <msnyder@redhat.com>Michael Snyder1-6/+43
2003-11-03 * interp.c (fsca_s, fsrra_s): New functions.Joern Rennecke1-0/+49
2003-10-15include/gdb:Joern Rennecke1-0/+11
2003-08-112003-08-11 Shrinivas Atre <shrinivasa@KPITCummins.com>Michael Snyder1-0/+52
2003-02-27Index: arm/ChangeLogAndrew Cagney1-3/+3
2002-10-11gcc uses trap 33 for profiling, but the simulator didn't support it.Joern Rennecke1-4/+15
2002-07-17include/gdb:Joern Rennecke1-114/+163
2002-06-18 * interp.c (sim_resume): Fix setting of bus error forJoern Rennecke1-1/+1
2002-06-09Move include/callback.h and include/remote-sim.h to include/gdb/.Andrew Cagney1-2/+2
2001-01-30* interp.c (sim_create_inferior): Record program arguments forAlexandre Oliva1-3/+45
2001-01-24* interp.c (trap): Implement time.Alexandre Oliva1-0/+3
2000-05-15sh-dsp support, simulator speedup by using host byte order:Joern Rennecke1-304/+891
1999-04-26import gdb-19990422 snapshotStan Shebs1-24/+213
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+1414
1999-04-16Initial creation of sourceware repositoryStan Shebs1-1663/+0
1997-09-02Comment typo fix.Joern Rennecke1-1/+1
1997-09-02Sanitation fixes.Joern Rennecke1-1/+41
1997-09-02Merge SH4 branch simulator in to devo.Andrew Cagney1-124/+448
1997-08-27Add ABFD argument to sim_create_inferior. Document.Andrew Cagney1-2/+6
1997-08-26Flush defunct sim_kill.Andrew Cagney1-7/+0
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