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AgeCommit message (Expand)AuthorFilesLines
2022-11-07sim: riscv: add missing AC_MSG_RESULT callMike Frysinger1-0/+1
2022-11-07sim: riscv: drop subdir configure logicMike Frysinger5-3129/+23
2022-11-05sim: run: move linking into top-levelMike Frysinger1-0/+25
2022-11-02sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger1-2/+2
2022-10-31sim: reg: constify store helperMike Frysinger1-1/+1
2022-10-31sim: common: change sim_read & sim_write to use void* buffersMike Frysinger1-5/+5
2022-10-23sim: mips/ppc/riscv: re-add AC_CANONICAL_SYSTEM [PR sim/29439]Mike Frysinger2-0/+162
2022-10-11sim/riscv: fix multiply instructions on simulatorTsukasa OI1-0/+1
2022-09-05sim/riscv: Complete tidying up with SBREAKTsukasa OI1-3/+3
2022-02-21sim: gdbinit: hoist setup to common codeMike Frysinger1-9/+0
2022-01-06sim: riscv: migrate to standard uintXX_t typesMike Frysinger1-28/+28
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker6-6/+6
2021-11-28sim: riscv: switch to new target-newlib-syscallMike Frysinger2-3/+2
2021-11-16sim: callback: expose argv & environMike Frysinger1-0/+5
2021-11-16sim: keep track of program environment stringsMike Frysinger1-0/+6
2021-11-15sim: split program path out of argv vectorMike Frysinger1-4/+1
2021-10-31sim: drop unused targ-vals.h includesMike Frysinger1-2/+0
2021-08-17sim: rename ChangeLog files to ChangeLog-2021Mike Frysinger1-0/+0
2021-07-01sim: unify reserved instruction bits settingsMike Frysinger2-2/+4
2021-06-30sim: unify scache settingsMike Frysinger2-2/+4
2021-06-30sim: move default model to the runtime sim stateMike Frysinger5-37/+8
2021-06-30sim: namespace sim_machsMike Frysinger3-1/+11
2021-06-29sim: model: constify sim_machs storageMike Frysinger2-1/+5
2021-06-22sim: drop configure scripts for simple portsMike Frysinger2-0/+11
2021-06-21sim: unify hardware settingsMike Frysinger3-49/+5
2021-06-21sim: hw: rework configure option & device selectionMike Frysinger2-37/+29
2021-06-20sim: delete SIM_AC_COMMON macroMike Frysinger4-5/+5
2021-06-20sim: unify general maintainer settingsMike Frysinger2-124/+0
2021-06-20sim: move sim-inline to the common codeMike Frysinger3-36/+5
2021-06-19sim: unify gettext/intl probing logicMike Frysinger2-85/+0
2021-06-19sim: unify toolchain dependency logicMike Frysinger2-1109/+1
2021-06-19sim: unify toolchain probing logicMike Frysinger2-1360/+26
2021-06-19sim: unify bfd library dependency testing logicMike Frysinger3-7691/+6
2021-06-19sim: unify various library testing logicMike Frysinger2-141/+6
2021-06-18sim: unify -Werror build settingsMike Frysinger3-112/+6
2021-06-18sim: move -Werror disabling to MakefileMike Frysinger2-5/+8
2021-06-18sim: split sim-signal.h include outMike Frysinger2-0/+5
2021-06-17sim: overhaul & unify endian settings managementMike Frysinger5-58/+11
2021-06-16sim: drop obsolete AC_EXEEXT callMike Frysinger2-2/+4
2021-06-16sim: drop arch-specific config.hMike Frysinger3-280/+47
2021-06-15sim: move dv-sockser define to CPPFLAGSMike Frysinger3-8/+5
2021-06-14sim: drop redundant SIM_AC_OPTION_WARNINGSMike Frysinger3-96/+100
2021-06-12sim: overhaul alignment settings managementMike Frysinger4-56/+8
2021-06-12sim: unify bug & package settingsMike Frysinger3-87/+2
2021-06-12sim: unify debug/stdio/trace/profile build settingsMike Frysinger2-150/+2
2021-06-12sim: unify environment build settingsMike Frysinger3-32/+2
2021-06-12sim: unify assert build settingsMike Frysinger4-28/+6
2021-06-12sim: unify platform function & header testsMike Frysinger3-552/+6
2021-05-17sim: fully merge sim_state_base into sim_stateMike Frysinger2-2/+4
2021-05-17sim: riscv: invert sim_state storageMike Frysinger4-12/+22
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