Age | Commit message (Collapse) | Author | Files | Lines | |
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2023-12-15 | sim: mn10300: fix incorrect implementation of a few insns | Mike Frysinger | 1 | -7/+7 | |
Fix a few problems caught by compiler warnings: * Some of the asr & lsr insns were setting up the c state flag, but then forgetting to set it in the PSW. Add it like the other asr & lsr variants. * Some of the dmulh insns were multiplying one of the source regs against itself instead of against the other source reg. * The sat16_cmp parallel insn was using the wrong register in the compare -- the reg1 src/dst pair are used in the sat16 op, and the reg2 src/dst pair are used in the add op. | |||||
2022-12-25 | sim: mn10300: fix SMP compile | Mike Frysinger | 1 | -4/+4 | |
The igen tool sets up the SD define for code fragments to use, but mn10300 was expecting "sd". Change all the igen related code to use SD so it actually compiles. | |||||
2022-01-06 | sim: mn10300: migrate to standard uintXX_t types | Mike Frysinger | 1 | -290/+290 | |
This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. | |||||
2011-06-20 | * am33.igen (sub Rm,Rn,Rd): Fix computation of carry flag. | Nick Clifton | 1 | -1/+1 | |
2004-06-26 | 2000-08-07 Graham Stott <grahams@cygnus.co.uk> | Alexandre Oliva | 1 | -0/+456 | |
* am33-2.igen (fmadd, fmsub, fmnadd, fmnsub): Correct typo. 2000-05-29 Alexandre Oliva <aoliva@cygnus.com> * interp.c (fpu_disabled_exception, fpu_unimp_exception, fpu_check_signal_exception): Take additional state arguments. Print exception type and call program_interrupt. Adjust callers. (fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div, fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Take additional arguments. * mn10300_sim.h (fpu_disabled_exception, fpu_unimp_exception, fpu_check_signal_exception): Adjust prototypes. (fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div, fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Likewise. * am33-2.igen: Adjust calls. 2000-05-19 Alexandre Oliva <aoliva@cygnus.com> * op_utils.c (cmp2fcc): Moved... * interp.c: ... here. 2000-05-18 Alexandre Oliva <aoliva@cygnus.com> * am33-2.igen: Use `unsigned32', `signed32', `unsigned64' or `signed64' where type width is relevant. 2000-05-15 Alexandre Oliva <aoliva@cygnus.com> * mn10300_sim.h: Include sim-fpu.h. (FD2FPU, FPU2FD): Enclose the FD argument in parentheses. (fpu_check_signal_exception): Declare. (struct fp_prec_t, fp_single_prec, fp_double_prec): Likewise. (FP_SINGLE, FP_DOUBLE): Shorthands for fp_*_prec. (fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div, fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Declare. * interp.c (fpu_disabled_exception): Document. (fpu_unimp_exception): Likewise. (fpu_check_signal_exception): Define. (reg2val_32, round_32, val2reg_32, fp_single_prec): Likewise. (reg2val_64, round_64, val2reg_64, fp_double_prec): Likewise. (REG2VAL, ROUND, VAL2REG): Define shorthands. (fpu_status_ok): Define. (fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div, fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Define. * am33-2.igen (frsqrt, fcmp, fadd, fsub, fmul, fdiv, fmadd, fmsub, fnmadd, fnmsub): Use new functions. 2000-04-27 Alexandre Oliva <aoliva@cygnus.com> * interp.c (sim_create_inferior): Set PSW bit to enable FP insns if architecture is AM33/2.0. * am33.igen: Include am33-2.igen. 2000-04-23 Alexandre Oliva <aoliva@cygnus.com> * mn10300.igen (movm, call, ret, retf): Check for am33_2 too. * am33.igen (movm): Likewise. 2000-04-19 Alexandre Oliva <aoliva@cygnus.com> * am33.igen: Added `*am33_2' to some instructions that were missing it. 2000-04-07 Alexandre Oliva <aoliva@cygnus.com> * am33-2.igen: New file. All insns implemented, but FP flags are only set for fcmp, exceptional conditions are not handled yet. * Makefile.in (IGEN_INSN): Added am33-2.igen. (tmp-igen): Added -M am33_2. * mn10300.igen, am33.igen: Added `*am33_2' to all insns. * gencode.c: Support FMT_D3. * mn10300_sim.h (dword): New type. (struct _state): Added fpregs. (REG_FPCR, FPCR): New define. All assorted bitmaps. (XS2FS, AS2FS, Xf2FD): New macros. (FS2FPU, FD2FPU, FPU2FS, FPU2FD): Likewise. (load_dword, store_dword): New functions or macros. (u642dw, dw2u64): New functions. (fpu_disabled_exception, fpu_unimp_exception): Declared. * interp.c (fpu_disabled_exception): Defined; no actual implementation. (fpu_unimp_exception): Likewise. * op_utils.c (cmp2fcc): New function. | |||||
2003-02-26 | Index: common/ChangeLog | Andrew Cagney | 1 | -1/+1 | |
2003-02-26 Andrew Cagney <cagney@redhat.com> * sim-engine.h (sim_engine_abort): Add noreturn attribute. (sim_engine_vabort): Ditto. (sim_engine_halt, sim_engine_restart): Ditto. Index: mn10300/ChangeLog 2003-02-26 Andrew Cagney <cagney@redhat.com> * am33.igen: Call sim_engine_abort instead of abort. | |||||
2000-08-09 | * am33.igen: Warning clean-up. | Alexandre Oliva | 1 | -42/+15 | |
(movm): Initialize PC and mask. (mov, movbu, movhu): Set srcreg2 from RI0. (bsch): Initialize c. (sat16_cmp): Actually do the comparison. (mov_llt): Do not overwrite dstreg with uninitialized variable. | |||||
2000-05-29 | minor formatting tweaks to aid syncronisation | Nick Clifton | 1 | -2/+5 | |
2000-05-22 | * am33.igen: Fix leading comments of SP-relative offset insns that | Alexandre Oliva | 1 | -7/+6 | |
referred to other registers. Make their offsets unsigned. | |||||
2000-05-18 | * mn10300_sim.h (genericAdd, genericSub, genericCmp, genericOr, | Alexandre Oliva | 1 | -104/+104 | |
genericXor, genericBtst): Use `unsigned32'. * op_utils.c: Likewise. * mn10300.igen, am33.igen: Use `unsigned32', `signed32', `unsigned64' or `signed64' where type width is relevant. | |||||
2000-04-25 | * am33.igen (inc4 Rn): Use genericAdd so as to modify flags. | Alexandre Oliva | 1 | -1/+1 | |
2000-04-09 | * am33.igen: Make SP-relative offsets unsigned. Add `*am33' for | Alexandre Oliva | 1 | -11/+29 | |
some instructions that were missing it. | |||||
1999-12-07 | import gdb-1999-12-06 snapshot | Jason Molenda | 1 | -0/+8683 | |
1999-04-16 | Initial creation of sourceware repository | Stan Shebs | 1 | -8411/+0 | |
1998-07-27 | * am33.igen: Detect cases where two operands must not match in | Jeff Law | 1 | -38/+42 | |
non-DSP instructions. | |||||
1998-07-24 | * am33.igen (translate_xreg): New function. Use it as needed. | Jeff Law | 1 | -28/+35 | |
1998-07-23 | * am33.igen: Add some missing instructions. | Jeff Law | 1 | -11/+238 | |
Missed a few last week... Grrr. | |||||
1998-07-23 | * am33.igen: Autoincrement loads/store fixes. | Jeff Law | 1 | -34/+253 | |
1998-07-21 | * am33.igen: Add most am33 DSP instructions. | Jeff Law | 1 | -15/+3530 | |
1998-07-09 | * am33.igen: Fix Z bit for remaining addc/subc instructions. | Jeff Law | 1 | -40/+47 | |
Do not sign extend immediate for mov imm,XRn. More random mul, mac & div fixes. Remove some unused variables. Sign extend 24bit displacement in memory addresses. Whee, more fixes. | |||||
1998-07-09 | * mn10300.igen: Fix Z bit for addc and subc instructions. | Jeff Law | 1 | -20/+25 | |
Minor fixes in multiply/divide patterns. start-sanitize-am33 * am33.igen: Fix Z bit for addc Rm,Rn and subc Rm,Rn. Various fixes to 2 register multiply, divide and mac instructions. Set Z,N correctly for sat16. Sign extend 24 bit immediate for add, and sub instructions. * am33.igen: Add remaining non-DSP instructions. end-sanitize-am33 | |||||
1998-07-09 | * am33.igen: Add remaining non-DSP instructions. | Jeff Law | 1 | -20/+686 | |
Lots of work still remains. PSW handing is probably broken badly and the mul/mac classes of instructions are probably not handled correctly. | |||||
1998-07-09 | * am33.igen (translate_rreg): New function. Use it as appropriate. | Jeff Law | 1 | -2335/+372 | |
1998-07-08 | * am33.igen: More am33 instructions. Fix "div". | Jeff Law | 1 | -88/+1622 | |
1998-07-06 | * am33.igen: Add many more am33 instructions. | Jeff Law | 1 | -84/+1927 | |
1998-07-01 | Tweak. | Jeff Law | 1 | -1/+14 | |
1998-07-01 | * am33.igen: New file with some am33 support. | Jeff Law | 1 | -0/+2334 | |
Checking in work-to-date. |