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AgeCommit message (Expand)AuthorFilesLines
2022-12-24sim: mips: move igen settings to top-level configureMike Frysinger4-3634/+278
2022-12-24sim: mips: namespace igen configure varsMike Frysinger3-209/+218
2022-12-24sim: mips: add igen recursive depMike Frysinger1-0/+3
2022-12-24sim: mips: drop unused ENGINE_ISSUE_POSTFIX_HOOKMike Frysinger2-8/+0
2022-12-24sim: igen: drop move-if-changed usageMike Frysinger1-178/+83
2022-12-22sim: move bfd.h include out of sim-main.hMike Frysinger1-1/+0
2022-12-22sim: mips: trim redundant igen settingsMike Frysinger2-18/+0
2022-12-22sim: mips: merge mips64* with existing multi-run buildMike Frysinger2-10/+4
2022-12-22sim: mips: merge mips64vr5000 with existing multi-run buildMike Frysinger2-8/+2
2022-12-22sim: mips: switch from SIM_ADDR to address_wordMike Frysinger2-31/+13
2022-12-22sim: mips: merge mips64vr4300 with existing multi-run buildMike Frysinger2-8/+2
2022-12-21sim: mips: match target on cpu settingsMike Frysinger2-26/+26
2022-12-21sim: mips: move fpu bitsize defines to top-level configureMike Frysinger5-69/+16
2022-12-21sim: mips: move bitsize defines to top-level configureMike Frysinger5-97/+18
2022-12-21sim: mips: move subtarget defines to top-level configureMike Frysinger4-41/+35
2022-12-21sim: mips: always resolve active bfd mach dynamicallyMike Frysinger3-106/+3
2022-12-21sim: build: hoist lists of hw devices upMike Frysinger2-2/+5
2022-12-21sim: enable common sim_cpu usage everywhereMike Frysinger1-2/+0
2022-12-21sim: mips: invert sim_cpu storageMike Frysinger2-73/+90
2022-11-08sim: mips: call Unpredictable instead of setting bogus values [PR sim/29276]Mike Frysinger1-2/+2
2022-11-05sim: run: move linking into top-levelMike Frysinger1-0/+25
2022-11-04sim: mips: simplify fpu configure logicMike Frysinger2-22/+14
2022-11-02sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger1-4/+4
2022-10-31sim: reg: constify store helperMike Frysinger1-2/+2
2022-10-31sim: common: change sim_read & sim_write to use void* buffersMike Frysinger1-15/+15
2022-10-23sim: mips/ppc/riscv: re-add AC_CANONICAL_SYSTEM [PR sim/29439]Mike Frysinger2-0/+162
2022-05-13sim: remove use of PTRAlan Modra1-2/+2
2022-02-21sim: gdbinit: hoist setup to common codeMike Frysinger1-9/+0
2022-02-04sim: mips: Add simulator support for mips32r6/mips64r6Faraz Shahbazker11-70/+2147
2022-02-04sim: Allow toggling of quiet NaN-bit semanticsFaraz Shahbazker3-3/+7
2022-01-06sim: mips: migrate to standard uintXX_t typesMike Frysinger17-1083/+1083
2022-01-01sim: mips: clean up bad style/whitespaceMike Frysinger23-345/+345
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker21-21/+21
2021-12-16sim: mips/or1k: drop redundant arg to bitsize macroMike Frysinger2-4/+2
2021-11-28sim: drop unused gentmap & nltvals.def logicMike Frysinger1-1/+1
2021-11-25sim: mips: avoid _ namespaceMike Frysinger1-3/+3
2021-11-15sim: split program path out of argv vectorMike Frysinger1-5/+1
2021-11-06sim: mips: use sim_fpu_to{32,64}u to fix build warningsTiezhu Yang2-7/+4
2021-11-03sim: mips: fix missing prototype in multi-run generationMike Frysinger2-0/+4
2021-11-01sim: mips: reduce -Wno-error scopeMike Frysinger2-8/+8
2021-10-31sim: igen: tighten up build outputMike Frysinger1-9/+9
2021-10-31sim: silence stamp touch rulesMike Frysinger1-6/+6
2021-10-31sim: standardize move-if-change rulesMike Frysinger1-103/+71
2021-10-31sim: mips/v850: remove redundant variable setupMike Frysinger1-5/+0
2021-09-09sim: mips: delete unused PSIZE defineMike Frysinger1-2/+0
2021-08-17sim: rename ChangeLog files to ChangeLog-2021Mike Frysinger1-0/+0
2021-07-01sim: unify reserved instruction bits settingsMike Frysinger4-27/+6
2021-06-30sim: unify scache settingsMike Frysinger1-2/+0
2021-06-30sim: move default model to the runtime sim stateMike Frysinger2-2/+4
2021-06-22sim: drop configure scripts for simple portsMike Frysinger2-0/+11
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