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AgeCommit message (Expand)AuthorFilesLines
2024-01-12Update copyright year range in header of all files managed by GDBAndrew Burgess1-1/+1
2023-12-21sim: mcore: fix Wimplicit-fallthrough warningsMike Frysinger1-0/+2
2023-12-19sim: mcore: fix -Wunused-variable warningsMike Frysinger1-4/+3
2023-12-18Yet another fix for mcore-sim (rotli)Jeff Law1-1/+1
2023-12-07sim: mcore: fix -Wunused-but-set-variable warningsMike Frysinger1-4/+0
2023-12-01Fix right shifts in mcore simulator on 64 bit hosts.Jeff Law1-2/+2
2023-10-11[RFA] Fix for mcore simulatorJeff Law1-4/+4
2023-01-18sim: info: convert verbose field to a boolMike Frysinger1-1/+1
2023-01-01Update copyright year range in header of all files managed by GDBJoel Brobecker1-1/+1
2022-12-25sim: cpu: change default init to handle all cpusMike Frysinger1-1/+1
2022-12-23sim: mcore: move arch-specific settings to internal headerMike Frysinger1-0/+2
2022-12-22sim: mcore: replace custom "word" type with int32_tMike Frysinger1-24/+24
2022-12-21sim: mcore: invert sim_cpu storageMike Frysinger1-23/+36
2022-11-02sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger1-2/+2
2022-10-31sim: reg: constify store helperMike Frysinger1-1/+1
2022-10-31sim: constify various integer readersMike Frysinger1-1/+1
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker1-1/+1
2021-11-28sim: mcore: switch to new target-newlib-syscallMike Frysinger1-0/+5
2021-11-15sim: split program path out of argv vectorMike Frysinger1-4/+1
2021-06-18sim: split sim-signal.h include outMike Frysinger1-0/+1
2021-05-16sim: switch config.h usage to defs.hMike Frysinger1-1/+3
2021-05-14sim: create header namespaceMike Frysinger1-2/+2
2021-05-04sim: mcore: fix build time warningsMike Frysinger1-1/+1
2021-05-04sim: remove sys/times.h in most placesMike Frysinger1-1/+0
2021-04-12sim: cgen: move cgen_cpu_max_extra_bytes logic into the common codeMike Frysinger1-1/+1
2021-01-01Update copyright year range in all GDB filesJoel Brobecker1-1/+1
2020-01-01Update copyright year range in all GDB files.Joel Brobecker1-1/+1
2019-01-01Update copyright year range in all GDB files.Joel Brobecker1-1/+1
2018-01-02Update copyright year range in all GDB filesJoel Brobecker1-1/+1
2017-01-01update copyright year range in GDB filesJoel Brobecker1-1/+1
2016-01-06sim: sim_{create_inferior,open,parse_args}: constify argv/env slightlyMike Frysinger1-2/+4
2016-01-03sim: parse_args: display getopt error ourselvesMike Frysinger1-3/+1
2016-01-01GDB copyright headers update after running GDB's copyright.py script.Joel Brobecker1-1/+1
2015-11-15sim: mcore: pull cpu state out of global scopeMike Frysinger1-293/+246
2015-11-15sim: mcore: switch to common sim-regMike Frysinger1-4/+6
2015-11-15sim: mcore: convert to common reason/resume logicMike Frysinger1-40/+47
2015-11-15sim: sim-close: unify sim_close logicMike Frysinger1-6/+0
2015-06-17sim: syscall: add common sim_syscall helpersMike Frysinger1-19/+3
2015-06-17sim: syscall: unify memory helpersMike Frysinger1-24/+3
2015-04-21sim: mcore: clean up printf warningsMike Frysinger1-8/+9
2015-04-21sim: mcore: convert to common memory/verbose functionsMike Frysinger1-319/+34
2015-04-21sim: mcore: drop watchpoint/dumpmem/clearstats supportMike Frysinger1-73/+6
2015-04-21sim: mcore: switch to common syscall handlingMike Frysinger1-140/+27
2015-04-17sim: replace CIA_{GET,SET} with CPU_PC_{GET,SET}Mike Frysinger1-4/+4
2015-04-16sim: avr/mcore/moxie: fill out sim-cpu pc fetch/store helpersMike Frysinger1-0/+16
2015-03-29sim: mcore/microblaze: delete dead codeMike Frysinger1-16/+0
2015-03-29sim: mcore: convert to nrunMike Frysinger1-112/+95
2015-03-29sim: mcore: drop sbrk supportMike Frysinger1-39/+3
2015-03-16sim: mcore/microblaze: strip trailing whitespaceMike Frysinger1-135/+135
2015-03-16sim: mcore/microblaze: clean up a bitMike Frysinger1-124/+50
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