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AgeCommit message (Expand)AuthorFilesLines
2023-01-10sim: modules: trigger generation from top-levelMike Frysinger1-0/+1
2023-01-02sim: build: move generated headers to built sourcesMike Frysinger1-1/+2
2023-01-02sim: lm32: hoist cgen rules to top-levelMike Frysinger2-22/+11
2023-01-01sim: replace -I$srcroot/opcodes include with -I$srcrootMike Frysinger1-2/+2
2023-01-01Update copyright year range in header of all files managed by GDBJoel Brobecker20-20/+20
2022-12-25sim: cpu: change default init to handle all cpusMike Frysinger1-1/+1
2022-12-23sim: lm32/m32r: drop redundant opcode/cgen.h includeMike Frysinger1-1/+0
2022-12-23sim: cgen: move symcat.h include to where it's usedMike Frysinger1-1/+0
2022-12-23sim: cgen: move cgen-types.h include to cgen-defs.hMike Frysinger1-1/+0
2022-12-22sim: use bfd_vma when reading start addr from bfd infoMike Frysinger1-1/+1
2022-12-21sim: build: hoist lists of hw devices upMike Frysinger2-4/+5
2022-12-21sim: enable common sim_cpu usage everywhereMike Frysinger1-2/+0
2022-12-21sim: lm32: invert sim_cpu storageMike Frysinger3-12/+7
2022-12-20sim: move register headers into sim/ namespace [PR sim/29869]Mike Frysinger1-1/+1
2022-11-05sim: run: move linking into top-levelMike Frysinger1-0/+8
2022-11-04sim: build: remove various obsolete generation dep variablesMike Frysinger1-9/+0
2022-11-04sim: cleanup unused SIM_EXTRA_CFLAGSMike Frysinger1-3/+0
2022-11-02sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger1-4/+2
2022-10-31sim: reg: constify store helperMike Frysinger1-1/+1
2022-10-24sim/lm32: fix some missing function declaration warningsAndrew Burgess4-3/+17
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker20-20/+20
2021-12-09sim: use ## for automake commentsMike Frysinger1-19/+19
2021-11-28sim: iq2000/lm32/m32c/moxie/rx: switch to new target-newlib-syscall.hMike Frysinger1-2/+2
2021-11-16sim: callback: expose argv & environMike Frysinger1-2/+7
2021-11-16sim: keep track of program environment stringsMike Frysinger1-1/+7
2021-11-15sim: split program path out of argv vectorMike Frysinger1-4/+1
2021-11-02sim: hoist cgen mloop rules up to common buildsMike Frysinger2-12/+38
2021-11-01sim: lm32: reduce -Wno-error scopeMike Frysinger3-5/+5
2021-10-31sim: tighten up stamp rulesMike Frysinger1-1/+2
2021-10-31sim: silence stamp touch rulesMike Frysinger1-3/+3
2021-10-31sim: standardize move-if-change rulesMike Frysinger1-2/+2
2021-08-17sim: rename ChangeLog files to ChangeLog-2021Mike Frysinger1-0/+0
2021-06-30sim: cris/frv/iq2000/lm32: merge with common configure scriptMike Frysinger4-2896/+6
2021-06-30sim: unify scache settingsMike Frysinger4-34/+7
2021-06-30sim: move default model to the runtime sim stateMike Frysinger5-24/+9
2021-06-30sim: namespace sim_machsMike Frysinger3-1/+11
2021-06-29sim: model: constify sim_machs storageMike Frysinger2-1/+5
2021-06-28sim: cgen: delete unused record_trace_results functionsMike Frysinger2-8/+4
2021-06-22sim: drop configure scripts for simple portsMike Frysinger2-0/+11
2021-06-21sim: unify hardware settingsMike Frysinger3-49/+5
2021-06-21sim: hw: rework configure option & device selectionMike Frysinger4-37/+32
2021-06-20sim: delete SIM_AC_COMMON macroMike Frysinger4-5/+5
2021-06-20sim: unify general maintainer settingsMike Frysinger3-124/+5
2021-06-20sim: unify cgen maintainer settingsMike Frysinger5-45/+6
2021-06-20sim: move sim-inline to the common codeMike Frysinger3-36/+5
2021-06-19sim: unify gettext/intl probing logicMike Frysinger2-85/+0
2021-06-19sim: unify toolchain dependency logicMike Frysinger2-1109/+1
2021-06-19sim: unify toolchain probing logicMike Frysinger2-1360/+26
2021-06-19sim: unify bfd library dependency testing logicMike Frysinger3-7691/+6
2021-06-19sim: unify various library testing logicMike Frysinger2-141/+6
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