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AgeCommit message (Expand)AuthorFilesLines
2022-12-23sim: cgen: move symcat.h include to where it's usedMike Frysinger1-1/+0
2022-12-23sim: cgen: move cgen-types.h include to cgen-defs.hMike Frysinger1-1/+0
2022-12-22sim: switch sim_{read,write} APIs to 64-bit all the time [PR sim/7504]Mike Frysinger1-2/+2
2022-12-22sim: use bfd_vma when reading start addr from bfd infoMike Frysinger1-2/+2
2022-12-21sim: build: hoist lists of hw devices upMike Frysinger2-4/+5
2022-12-21sim: enable common sim_cpu usage everywhereMike Frysinger1-2/+0
2022-12-21sim: cris: invert sim_cpu storageMike Frysinger6-239/+244
2022-11-05sim: run: move linking into top-levelMike Frysinger1-0/+8
2022-11-05sim: cris: move rvdummy linking to top-levelMike Frysinger2-12/+8
2022-11-04sim: build: remove various obsolete generation dep variablesMike Frysinger1-20/+0
2022-11-04sim: build: switch to libtool for linkingMike Frysinger1-1/+2
2022-11-02sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger1-4/+4
2022-10-31sim: reg: constify store helperMike Frysinger2-2/+2
2022-10-31sim: common: change sim_read & sim_write to use void* buffersMike Frysinger1-1/+1
2022-10-11sim/cris: Add ATTRIBUTE_PRINTFTsukasa OI1-1/+1
2022-08-06Don't use BFD_VMA_FMT in gdb and simAlan Modra1-12/+13
2022-06-15sim: fix BFD_VMA format arguments on 32-bit hosts [PR gdb/29184]Sergei Trofimovich1-4/+6
2022-05-13sim: remove use of PTRAlan Modra2-3/+3
2022-04-04sim: fixes for libopcodes styled disassemblerAndrew Burgess1-1/+2
2022-02-14sim cris: Unbreak --disable-sim-hardware buildsHans-Peter Nilsson1-0/+8
2022-02-14sim cris: Correct PRIu32 to PRIx32Hans-Peter Nilsson1-1/+1
2022-01-06sim: cris: migrate to standard uintXX_t typesMike Frysinger7-80/+80
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker29-29/+29
2021-12-09sim: use ## for automake commentsMike Frysinger1-22/+22
2021-11-16sim: callback: expose argv & environMike Frysinger1-4/+12
2021-11-16sim: keep track of program environment stringsMike Frysinger1-2/+8
2021-11-15sim: cris: touch up rvdummy handlingMike Frysinger1-2/+2
2021-11-15sim: split program path out of argv vectorMike Frysinger1-7/+3
2021-11-08sim: cris: clean up missing func prototype warningsMike Frysinger4-6/+6
2021-11-03sim: mloop: mark a few conditionally used funcs as unusedMike Frysinger1-1/+2
2021-11-02sim: hoist cgen mloop rules up to common buildsMike Frysinger2-31/+55
2021-11-01sim: cris: reduce -Wno-error scopeMike Frysinger1-2/+2
2021-10-31sim: tighten up stamp rulesMike Frysinger1-2/+4
2021-10-31sim: silence stamp touch rulesMike Frysinger1-5/+5
2021-10-31sim: standardize move-if-change rulesMike Frysinger1-6/+6
2021-08-17sim: rename ChangeLog files to ChangeLog-2021Mike Frysinger1-0/+0
2021-06-30sim: cris/frv/iq2000/lm32: merge with common configure scriptMike Frysinger4-2896/+6
2021-06-30sim: unify scache settingsMike Frysinger4-34/+7
2021-06-30sim: move default model to the runtime sim stateMike Frysinger5-28/+9
2021-06-30sim: namespace sim_machsMike Frysinger3-1/+11
2021-06-29sim: cris: remove cgen-ops.h include hackMike Frysinger2-4/+5
2021-06-29sim: model: constify sim_machs storageMike Frysinger2-1/+5
2021-06-28sim: cgen: delete unused record_trace_results functionsMike Frysinger3-16/+5
2021-06-27sim: bpf/cris: include cgen-mem in decodersMike Frysinger3-0/+7
2021-06-24sim: cris: fix a few missing prototype warningsMike Frysinger3-32/+11
2021-06-23sim: cris: override getpid callbackMike Frysinger2-0/+13
2021-06-22sim: cris: fix a few warningsMike Frysinger2-2/+9
2021-06-22sim: drop configure scripts for simple portsMike Frysinger2-0/+11
2021-06-21sim: unify hardware settingsMike Frysinger3-49/+5
2021-06-21sim: hw: rework configure option & device selectionMike Frysinger4-52/+47
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