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2022-12-16x86: change representation of extension opcodeJan Beulich3-2286/+2288
2022-12-12x86: further re-work insn/suffix recognition to also cover MOVSXJan Beulich2-945/+892
2022-12-12x86: drop (now) stray IsStringJan Beulich2-26/+26
2022-12-12x86: re-work insn/suffix recognitionJan Beulich2-1290/+1118
2022-12-12x86: revert disassembler parts of "x86: Allow 16-bit register source for LAR ...Jan Beulich1-2/+14
2022-12-12x86: generate template sets data at build timeJan Beulich2-1/+2350
2022-12-12x86: drop sentinel from i386_optab[]Jan Beulich2-23/+0
2022-12-12x86: remove i386-opc.cJan Beulich5-36/+8
2022-12-12x86: instantiate i386_{op,reg}tab[] in gas instead of in libopcodesJan Beulich4-13/+7
2022-12-07PowerPC: Add support for RFC02655 - Saturating Subtract InstructionPeter Bergner1-0/+9
2022-12-07PowerPC: Add support for RFC02656 - Enhanced Load Store with Length InstructionsPeter Bergner1-0/+13
2022-12-06x86: Remove unnecessary vex.w check for xh_mode in disassemblerHaochen Jiang1-17/+12
2022-12-05libopcodes/mips: add support for disassembler stylingAndrew Burgess2-109/+201
2022-12-05opcodes/mips: use .word/.short for undefined instructionsAndrew Burgess1-3/+6
2022-12-03x86: Allow 16-bit register source for LAR and LSLH.J. Lu3-18/+6
2022-12-02x86: drop most OPERAND_TYPE_* (and rework the rest)Jan Beulich2-287/+0
2022-12-02x86: also use D for XCHG and TESTJan Beulich2-57/+9
2022-12-01opcodes: Remove i386-init.h and i386-tbl.h from HFILESH.J. Lu3-6/+0
2022-12-01x86: drop No_ldSufJan Beulich4-11598/+11594
2022-12-01x86/Intel: drop LONG_DOUBLE_MNEM_SUFFIXJan Beulich2-4/+4
2022-12-01x86/Intel: restrict use of LONG_DOUBLE_MNEM_SUFFIXJan Beulich2-8/+8
2022-11-30x86: clean up after removal of support for gcc <= 2.8.1Jan Beulich2-36/+5
2022-11-30x86: drop FloatRJan Beulich4-11255/+11187
2022-11-28RISC-V: Better support for long instructions (disassembler)Tsukasa OI1-5/+9
2022-11-24x86: widen applicability and use of CheckRegSizeJan Beulich2-14/+14
2022-11-24x86: add missing CheckRegSizeJan Beulich2-6/+6
2022-11-24x86: correct handling of LAR and LSLJan Beulich3-6/+50
2022-11-24PR16995, m68k coldfire emac immediate to macsr incorrect disassemblyAlan Modra1-2/+2
2022-11-22opcodes: Correct address for ARC's "isa_config" aux regShahab Vahedi2-1/+7
2022-11-17opcodes: Define NoSuf in i386-opc.tblH.J. Lu1-1847/+1848
2022-11-17i386: Move i386_seg_prefixes to gasH.J. Lu2-11/+0
2022-11-17RISC-V: Add T-Head Int vendor extensionChristoph Müllner1-0/+4
2022-11-17RISC-V: Add T-Head Fmv vendor extensionChristoph Müllner1-0/+4
2022-11-15Add AMD znver4 processor supportTejas Joshi6-4052/+4129
2022-11-14aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira6-49/+166
2022-11-14x86: fold special-operand insn attributes into a single enumJan Beulich4-11219/+11210
2022-11-12PowerPC64 paddi -MrawAlan Modra1-10/+10
2022-11-11x86: drop stray IsString from PadLock insnsJan Beulich2-32/+32
2022-11-10[opcodes/arm] Fix potential null pointer dereferencesLuis Machado1-1/+5
2022-11-09RISC-V: xtheadfmemidx: Use fp register in mnemonicsChristoph Müllner1-8/+8
2022-11-08PowerPC: Add XSP operand definePeter Bergner1-5/+6
2022-11-08x86: Correct wrong comments in vex_w_tableHaochen Jiang1-1/+1
2022-11-08Support Intel RAO-INTKong Lingling6-4174/+4278
2022-11-04opcodes/arm: silence compiler warning about uninitialized variable useAndrew Burgess1-1/+3
2022-11-04Support Intel AVX-NE-CONVERTkonglin16-4169/+4397
2022-11-04i386: Rename <xy> template.konglin11-17/+18
2022-11-02x86: drop bogus TbyteJan Beulich2-4/+4
2022-11-02Support Intel MSRLISTHu, Lin16-4161/+4237
2022-11-02Support Intel WRMSRNSHu, Lin16-4160/+4212
2022-11-02Support Intel CMPccXADDHaochen Jiang6-4150/+4805
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