| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2019-12-17 | S/390: Add support for z15 as CPU name. | Andreas Krebbel | 1 | -1/+2 |
| 2019-08-22 | [AArch64][gas] Update MTE system register encodings | Kyrylo Tkachov | 2 | -10/+19 |
| 2019-07-24 | [AArch64] Add support for GMID_EL1 register for +memtag | Kyrylo Tkachov | 2 | -1/+11 |
| 2019-07-02 | [AArch64] Allow MOVPRFX to be used with FMOV | Richard Sandiford | 2 | -1/+6 |
| 2019-07-02 | [AArch64] Add missing C_MAX_ELEM flags for SVE conversions | Richard Sandiford | 2 | -28/+33 |
| 2019-07-02 | [AArch64] Fix bogus MOVPRFX warning for GPR form of CPY | Richard Sandiford | 2 | -5/+5 |
| 2019-04-16 | [BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions | Sudakshina Das | 6 | -165/+189 |
| 2019-04-16 | [BINUTILS, AArch64, 1/2] Add new LDGM/STGM instruction | Sudakshina Das | 5 | -1541/+1575 |
| 2019-04-01 | AArch64: Fix disassembler bug with out-of-order sections | Tamar Christina | 3 | -155/+179 |
| 2019-03-12 | S/390: arch13: Adjust to recent changes | Andreas Krebbel | 2 | -5/+13 |
| 2019-03-12 | S/390: arch13: Add instruction descriptions | Andreas Krebbel | 2 | -101/+122 |
| 2019-02-07 | Arm: Backport hlt to all architectures. | Tamar Christina | 2 | -1/+6 |
| 2019-02-07 | Updated Swedish translation for the opcodes sub-directory | Nick Clifton | 2 | -308/+352 |
| 2019-02-02 | Restore 2.32 branch to development status | Nick Clifton | 3 | -11/+16 |
| 2019-02-02 | Set to 2.32 release version and regenerate configure and pot filesbinutils-2_32 | Nick Clifton | 3 | -70/+76 |
| 2019-01-31 | S/390: Implement instruction set extensions | Andreas Krebbel | 4 | -0/+120 |
| 2019-01-25 | AArch64: Add missing changelog for Update encodings for stg, st2g, stzg and s... | Tamar Christina | 1 | -0/+9 |
| 2019-01-25 | AArch64: Update encodings for stg, st2g, stzg and st2zg. | Sudi Das | 1 | -10/+10 |
| 2019-01-25 | AArch64: Add new STZGM instruction for Armv8.5-A Memory Tagging Extension. | Sudi Das | 5 | -1580/+1599 |
| 2019-01-25 | AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte... | Sudi Das | 10 | -1709/+1658 |
| 2019-01-23 | Fix changelog entry. | Nick Clifton | 1 | -0/+1 |
| 2019-01-23 | Updated translations for some binutils sub-directories. | Nick Clifton | 2 | -305/+351 |
| 2019-01-22 | [MIPS] fix typo in mips_arch_choices. | Chenghua Xu | 2 | -3/+7 |
| 2019-01-21 | Updated translations for vatious binutils subdirectories | Nick Clifton | 3 | -609/+696 |
| 2019-01-19 | Change to version 2.31.90 and regenerate configure and pot files. | Nick Clifton | 3 | -263/+304 |
| 2019-01-19 | Add markers for 2.32 branch to NEWS and ChangeLog files. | Nick Clifton | 1 | -0/+4 |
| 2019-01-13 | Add RXv3 instructions. | Yoshinori Sato | 3 | -1569/+5442 |
| 2019-01-09 | S12Z: Don't crash when disassembling invalid instructions. | John Darrington | 2 | -3/+5 |
| 2019-01-09 | S12Z: Fix disassembly of indexed OPR operands with zero index. | John Darrington | 2 | -30/+32 |
| 2019-01-09 | Adjust bfd/warning.m4 egrep patterns | Andrew Paprocki | 2 | -5/+9 |
| 2019-01-07 | s12z regen | Alan Modra | 3 | -3/+9 |
| 2019-01-03 | S12Z: opcodes: Separate the decoding of operations from their display. | John Darrington | 8 | -2548/+3241 |
| 2019-01-01 | Update year range in copyright notice of binutils files | Alan Modra | 269 | -272/+276 |
| 2019-01-01 | ChangeLog rotation | Alan Modra | 2 | -2538/+2552 |
| 2018-12-28 | PR24028, PPC_INT_FMT | Alan Modra | 2 | -10/+16 |
| 2018-12-18 | Include bfd_stdint.h in bfd.h | Alan Modra | 8 | -6/+17 |
| 2018-12-07 | RISC-V: Fix 4-arg add parsing. | Jim Wilson | 2 | -1/+6 |
| 2018-12-06 | sim/opcodes: Allow use of out of tree cgen source directory | Andrew Burgess | 3 | -8/+26 |
| 2018-12-06 | opcodes/riscv: Hide '.L0 ' fake symbols | Andrew Burgess | 3 | -0/+28 |
| 2018-12-03 | RISC-V: Accept version, supervisor ext and more than one NSE for -march. | Jim Wilson | 2 | -1/+6 |
| 2018-12-03 | [aarch64] - Only use MOV for disassembly when shifter op is LSL #0 | Egeyar Bagcioglu | 2 | -1/+8 |
| 2018-11-29 | RISC-V: Add missing c.unimp instruction. | Jim Wilson | 2 | -1/+7 |
| 2018-11-27 | RISC-V: Add .insn CA support. | Jim Wilson | 2 | -2/+12 |
| 2018-11-21 | S12Z opcodes: Fix bug disassembling certain shift instructions. | John Darrington | 2 | -19/+30 |
| 2018-11-13 | opcodes/nfp: Fix disassembly of crc[] with swapped operands. | Francois H. Theron | 2 | -6/+10 |
| 2018-11-12 | [BINUTILS, AARCH64, 8/8] Add data cache instructions for Memory Tagging Exten... | Sudakshina Das | 2 | -0/+48 |
| 2018-11-12 | [BINUTILS, AARCH64, 7/8] Add system registers for Memory Tagging Extension | Sudakshina Das | 2 | -0/+35 |
| 2018-11-12 | [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension | Sudakshina Das | 10 | -1642/+1724 |
| 2018-11-12 | [BINUTILS, AARCH64, 5/8] Add Tag getting instruction in Memory Tagging Extension | Sudakshina Das | 5 | -1607/+1633 |
| 2018-11-12 | [BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten... | Sudakshina Das | 8 | -1841/+2036 |
