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2015-07-21Release 2.25.1, add generated filesbinutils-2_25_1Tristan Gingold2-10/+14
2015-07-10Remove ppc860, ppc750cl, ppc7450 insns from common ppc.Alan Modra3-5/+16
2015-07-10PPC sync instruction accepts invalid and incompatible operandsPeter Bergner2-13/+47
2015-07-10Allow for optional operands with non-zero default values.Peter Bergner3-26/+33
2015-07-10Remove unused MTMSRD_L macro and re-add accidentally deleted comment.Peter Bergner2-2/+6
2015-07-10Add hwsync extended mnemonic.Peter Bergner2-0/+4
2015-07-10powerpc: Only initialise opcode indices onceAnton Blanchard2-25/+33
2015-07-10powerpc: Add slbfee. instructionAnton Blanchard2-0/+8
2015-06-16[AArch64] Backport support id_mmfr4 system registerJiong Wang2-0/+8
2015-05-14Fix some PPC assembler errors.Peter Bergner2-3/+18
2015-05-07[AArch64][Backport] Remove Load/Store register (unscaled immediate) aliasRenlin Li5-490/+442
2015-04-28opcodes/Peter Bergner2-12/+37
2015-03-11[ARM] Backport "Skip private symbol when doing objdump"Jiong Wang2-2/+9
2014-12-23Bump to version 2.25.0Tristan Gingold2-10/+14
2014-12-23Add generated files.binutils-2_25Tristan Gingold16-0/+0
2014-12-23Version 2.25Tristan Gingold2-10/+14
2014-12-19Add in a JALRC alias and fix the NAL instruction.Matthew Fortune2-1/+7
2014-11-30Power4 should treat mftb as extended mfspr mnemonicAlan Modra2-6/+11
2014-11-30Don't deprecate powerpc mftb insnAlan Modra2-7/+15
2014-11-17Add AVX512VBMI instructionsIlya Tocar8-5445/+5730
2014-11-17Add AVX512IFMA instructionsIlya Tocar8-5512/+5677
2014-11-17Add pcommit instructionIlya Tocar7-5262/+10575
2014-11-17Add clwb instructionIlya Tocar7-5260/+5310
2014-11-03Import updated translations provided by the Translation Project:Nick Clifton2-146/+372
2014-10-29Updated and New translations from the Translation Project.Nick Clifton2-270/+1059
2014-10-28ppc: enable msgclr and msgsnd on Power8Jan Beulich2-2/+8
2014-10-15Regenerate configure (after change of version)Tristan Gingold2-10/+14
2014-10-09This is a series of patches that add support for the SPARC M7 cpu toJose E. Marchesi3-1441/+1507
2014-09-22Ignore MOD field for control/debug register moveH.J. Lu2-32/+19
2014-09-16NDS32/opcodes: Add audio ISA extension and modify the disassemble implemnt.Kuan-Lin Chen4-1842/+2327
2014-09-15Add support for MIPS R6.Andrew Bennett4-362/+786
2014-09-10Properly handle suffix for iret and sysretH.J. Lu2-21/+59
2014-09-03[PATCH/AArch64] Generic support for all system registers using mrs and msrJiong Wang3-101/+28
2014-09-03[PATCH/AArch64] Implement LSE featureJiong Wang10-223/+2033
2014-08-26MIPS: Make the CODE10 operand code consistent between ISAsMaciej W. Rozycki2-5/+11
2014-08-22ARM/opcodes: Fix negative hexadecimal offset disassemblyMaciej W. Rozycki2-0/+8
2014-08-21MIPS/opcodes: Remove microMIPS 48-bit LI instructionMaciej W. Rozycki2-4/+5
2014-08-19This patch set mainly aims at improving the S/390 disassembler'sAndreas Arnez2-134/+184
2014-08-14opcodes: blackfin: convert ad-hoc ints to bfd_booleanMike Frysinger2-21/+31
2014-08-14opcodes: blackfin: simplify decode_CC2stat_0 logicMike Frysinger2-41/+11
2014-08-14opcodes: blackfin: avoid duplicate memory readsMike Frysinger2-6/+10
2014-08-13opcodes: blackfin: push down global stateMike Frysinger2-43/+83
2014-08-13opcodes: blackfin: do not force align the PCMike Frysinger2-1/+14
2014-08-13opcodes: blackfin: handle memory read errorsMike Frysinger2-19/+45
2014-07-29[MIPS] Rename COPROC related macrosMatthew Fortune3-134/+142
2014-07-29[MIPS] Implement O32 FPXX, FP64 and FP64A ABI extensionsMatthew Fortune3-24/+34
2014-07-22Add AVX512DQ instructions and their AVX512VL variants.Ilya Tocar8-5910/+9526
2014-07-22Add support for AVX512BW instructions and their AVX512VL versions.Ilya Tocar8-5277/+12632
2014-07-22Add support for AVX512VL versions of AVX512CD instructions.Ilya Tocar3-0/+214
2014-07-22Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions.Ilya Tocar7-4322/+20266
generated by cgit v1.1 at 2024-10-02 07:27:37 +0000