rocket-tools/riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-09-07	RISC-V: Clarify the naming rules of vendor operands.	Nelson Chu	1	-65/+65
2023-09-05	RISC-V: fold duplicate code in vector_macro()	Jan Beulich	1	-2/+2
2023-09-01	RISC-V: move various alias entries	Jan Beulich	1	-35/+35
2023-08-30	RISC-V: Make XVentanaCondOps RV64 only	Tsukasa OI	1	-2/+2
2023-08-15	RISC-V: Make "fli.h" available to 'Zvfh' + 'Zfa'	Tsukasa OI	1	-1/+1
2023-08-15	RISC-V: Add support for the 'Zihintntl' extension	Tsukasa OI	1	-0/+12
2023-08-15	RISC-V: remove indirection from register tables	Jan Beulich	1	-6/+6
2023-08-11	RISC-V: Fix opcode entries of "vmsge{,u}.vx"	Tsukasa OI	1	-4/+4
2023-08-07	RISC-V: move comment describing rules for riscv_opcodes[]	Jan Beulich	1	-10/+10
2023-08-02	Revert "2.41 Release sources"	Sam James	1	-0/+28
2023-08-02	2.41 Release sourcesbinutils-2_41-release	Nick Clifton	1	-28/+0
2023-07-18	RISC-V: Supports Zcb extension.	Jiawei	1	-0/+28
2023-07-01	RISC-V: Add support for the Zvksh ISA extension	Christoph Müllner	1	-0/+4
2023-07-01	RISC-V: Add support for the Zvksed ISA extension	Christoph Müllner	1	-0/+5
2023-07-01	RISC-V: Add support for the Zvknh[a,b] ISA extensions	Christoph Müllner	1	-0/+5
2023-07-01	RISC-V: Add support for the Zvkned ISA extension	Christoph Müllner	1	-0/+13
2023-07-01	RISC-V: Add support for the Zvkg ISA extension	Christoph Müllner	1	-0/+4
2023-07-01	RISC-V: Add support for the Zvbc extension	Nathan Huckleberry	1	-0/+6
2023-07-01	RISC-V: Add support for the Zvbb ISA extension	Christoph Müllner	1	-0/+18
2023-06-30	RISC-V: Add support for the Zfa extension	Christoph Müllner	1	-0/+64
2023-06-27	RISC-V: Support Zicond extension	Philipp Tomsich	1	-0/+4
2023-06-01	RISC-V: PR30449, Add lga assembler macro support.	Jim Wilson	1	-0/+1
2023-04-26	RISC-V: Support XVentanaCondOps extension	Philipp Tomsich	1	-0/+4
2023-03-31	RISC-V: Allocate "various" operand type	Tsukasa OI	1	-3/+3
2023-01-31	RISC-V: make C-extension JAL available again for (32-bit) assembly	Jan Beulich	1	-1/+1
2023-01-01	Update year range in copyright notice of binutils files	Alan Modra	1	-1/+1
2022-11-17	RISC-V: Add T-Head Int vendor extension	Christoph Müllner	1	-0/+4
2022-11-17	RISC-V: Add T-Head Fmv vendor extension	Christoph Müllner	1	-0/+4
2022-11-09	RISC-V: xtheadfmemidx: Use fp register in mnemonics	Christoph Müllner	1	-8/+8
2022-10-14	RISC-V: Move standard hints before all instructions	Tsukasa OI	1	-4/+8
2022-10-14	RISC-V: Move certain arrays to riscv-opc.c	Tsukasa OI	1	-0/+13
2022-10-04	RISC-V: Renamed INSN_CLASS for floating point in integer extensions.	Nelson Chu	1	-222/+222
2022-10-03	RISC-V: Move supervisor instructions after all unprivileged ones	Tsukasa OI	1	-32/+32
2022-09-30	RISC-V: Relax "fmv.[sdq]" requirements	Tsukasa OI	1	-3/+3
2022-09-30	RISC-V: drop stray INSN_ALIAS flags	Jan Beulich	1	-3/+3
2022-09-30	RISC-V: re-arrange opcode table for consistent alias handling	Jan Beulich	1	-38/+38
2022-09-23	RISC-V: Add Zawrs ISA extension support	Christoph Müllner	1	-0/+4
2022-09-22	RISC-V: Add T-Head MemPair vendor extension	Christoph Müllner	1	-0/+24
2022-09-22	RISC-V: Add T-Head MemIdx vendor extension	Christoph Müllner	1	-0/+60
2022-09-22	RISC-V: Add T-Head FMemIdx vendor extension	Christoph Müllner	1	-0/+10
2022-09-22	RISC-V: Add T-Head MAC vendor extension	Christoph Müllner	1	-0/+8
2022-09-22	RISC-V: Add T-Head CondMov vendor extension	Christoph Müllner	1	-0/+4
2022-09-22	RISC-V: Add T-Head Bitmanip vendor extension	Christoph Müllner	1	-0/+17
2022-09-22	RISC-V: Add T-Head SYNC vendor extension	Christoph Müllner	1	-0/+7
2022-09-22	RISC-V: Add T-Head CMO vendor extension	Christoph Müllner	1	-0/+25
2022-08-30	RISC-V: Add 'Zmmul' extension in assembler.	Tsukasa OI	1	-13/+13
2022-07-07	RISC-V: Added Zfhmin and Zhinxmin.	Tsukasa OI	1	-63/+63
2022-06-22	RISC-V: Use single h extension to control hypervisor CSRs and instructions.	Nelson Chu	1	-19/+19
2022-05-30	RISC-V: Add zhinx extension supports.	jiawei	1	-56/+56
2022-05-20	RISC-V: Update zfinx implement with zicsr.	Jia-Wei Chen	1	-14/+14