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path: root/opcodes/i386-tbl.h
AgeCommit message (Expand)AuthorFilesLines
2023-09-27x86: fold FMA VEX and EVEX templatesJan Beulich1-1157/+497
2023-09-27x86: fold VAES/VPCLMULQDQ VEX and EVEX templatesJan Beulich1-299/+198
2023-09-27x86: fold certain VEX and EVEX templatesJan Beulich1-955/+621
2023-09-15x86: fold CpuLM and Cpu64Jan Beulich1-2188/+2188
2023-09-14x86: support AVX10.1 vector size restrictionsJan Beulich1-3846/+7692
2023-09-14x86: make AES/PCMULQDQ respectively prereqs of VAES/VPCMULQDQJan Beulich1-290/+290
2023-09-01x86: drop Size64 from VMOVQJan Beulich1-1/+1
2023-08-11x86: pack CPU flags in opcode tableJan Beulich1-30768/+3846
2023-08-02Revert "2.41 Release sources"Sam James1-4415/+8525
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton1-8525/+4415
2023-07-27Support Intel PBNDKBHu, Lin11-3923/+3938
2023-07-27Support Intel SM4Haochen Jiang1-4439/+4477
2023-07-27Support Intel SM3Haochen Jiang1-4617/+4676
2023-07-27Support Intel SHA512Haochen Jiang1-4697/+4750
2023-07-27Support Intel AVX-VNNI-INT16konglin11-3991/+7936
2023-07-04x86: optimize 128-bit VPBROADCASTQ to VPUNPCKLQDQJan Beulich1-2/+2
2023-07-04x86: optimize pre-AVX512 {,V}PCMPGT* with identical sourcesJan Beulich1-15/+15
2023-07-04x86: optimize pre-AVX512 {,V}PCMPEQQ with identical sourcesJan Beulich1-3/+3
2023-06-16x86: shrink Masking insn attribute to a single bit (boolean)Jan Beulich1-1057/+1057
2023-05-23Support Intel FRED LKGSZhang, Jun1-3913/+3967
2023-04-07Support Intel AMX-COMPLEXHaochen Jiang1-3900/+3936
2023-03-31x86: introduce .insn directiveJan Beulich1-0/+1
2023-03-20x86: VexVVVV is now merely a booleanJan Beulich1-49/+49
2023-03-20x86: re-work build_modrm_byte()'s register assignmentJan Beulich1-44/+44
2023-02-24x86: MONITOR/MWAIT are not SSE3 insnsJan Beulich1-6613/+6613
2023-02-24x86-64: don't permit LAHF/SAHF with "generic64"Jan Beulich1-4727/+4751
2023-02-24x86: have insns acting on segment selector values allow for consistent operandsJan Beulich1-892/+954
2023-02-24x86: restrict insn templates accepting negative 8-bit immediatesJan Beulich1-96/+96
2023-02-22x86-64: LAR and LSL don't need REX.WJan Beulich1-4/+4
2023-02-22x86: optimize BT{,C,R,S} $imm,%regJan Beulich1-4/+4
2023-02-14x86: {LD,ST}TILECFG use an extension opcodeJan Beulich1-2/+2
2023-02-13PR30120: fix x87 fucomp misassembledMichael Matz1-1/+1
2023-02-10x86: drop use of VEX3SOURCESJan Beulich1-7636/+3818
2023-02-10x86: drop use of XOP2SOURCESJan Beulich1-24/+24
2023-02-10x86: limit use of XOP2SOURCESJan Beulich1-4/+4
2023-02-10x86: move (and rename) opcodespace attributeJan Beulich1-10947/+10947
2023-01-27x86: use ModR/M for FPU insns with operandsJan Beulich1-142/+142
2023-01-20x86: re-use insn mnemonic strings as much as possibleJan Beulich1-2211/+1860
2023-01-20x86: move insn mnemonics to a separate tableJan Beulich1-3818/+6144
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2022-12-16x86: change representation of extension opcodeJan Beulich1-2/+2
2022-12-12x86: further re-work insn/suffix recognition to also cover MOVSXJan Beulich1-937/+889
2022-12-12x86: drop (now) stray IsStringJan Beulich1-13/+13
2022-12-12x86: re-work insn/suffix recognitionJan Beulich1-1275/+1114
2022-12-12x86: generate template sets data at build timeJan Beulich1-0/+2329
2022-12-12x86: drop sentinel from i386_optab[]Jan Beulich1-13/+0
2022-12-12x86: instantiate i386_{op,reg}tab[] in gas instead of in libopcodesJan Beulich1-3/+3
2022-12-03x86: Allow 16-bit register source for LAR and LSLH.J. Lu1-2/+2
2022-12-02x86: also use D for XCHG and TESTJan Beulich1-51/+6
2022-12-01x86: drop No_ldSufJan Beulich1-11149/+11149
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