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path: root/opcodes/i386-opc.tbl
AgeCommit message (Expand)AuthorFilesLines
2022-12-16x86: change representation of extension opcodeJan Beulich1-2281/+2280
2022-12-12x86: further re-work insn/suffix recognition to also cover MOVSXJan Beulich1-8/+3
2022-12-12x86: drop (now) stray IsStringJan Beulich1-13/+13
2022-12-12x86: re-work insn/suffix recognitionJan Beulich1-15/+4
2022-12-03x86: Allow 16-bit register source for LAR and LSLH.J. Lu1-2/+2
2022-12-02x86: also use D for XCHG and TESTJan Beulich1-6/+3
2022-12-01x86: drop No_ldSufJan Beulich1-445/+445
2022-12-01x86/Intel: drop LONG_DOUBLE_MNEM_SUFFIXJan Beulich1-2/+2
2022-12-01x86/Intel: restrict use of LONG_DOUBLE_MNEM_SUFFIXJan Beulich1-4/+4
2022-11-30x86: clean up after removal of support for gcc <= 2.8.1Jan Beulich1-4/+3
2022-11-30x86: drop FloatRJan Beulich1-8/+4
2022-11-24x86: widen applicability and use of CheckRegSizeJan Beulich1-7/+7
2022-11-24x86: add missing CheckRegSizeJan Beulich1-3/+3
2022-11-24x86: correct handling of LAR and LSLJan Beulich1-2/+4
2022-11-17opcodes: Define NoSuf in i386-opc.tblH.J. Lu1-1847/+1848
2022-11-15Add AMD znver4 processor supportTejas Joshi1-0/+7
2022-11-14x86: fold special-operand insn attributes into a single enumJan Beulich1-2/+11
2022-11-11x86: drop stray IsString from PadLock insnsJan Beulich1-16/+16
2022-11-08Support Intel RAO-INTKong Lingling1-0/+9
2022-11-04Support Intel AVX-NE-CONVERTkonglin11-0/+12
2022-11-04i386: Rename <xy> template.konglin11-17/+18
2022-11-02x86: drop bogus TbyteJan Beulich1-2/+2
2022-11-02Support Intel MSRLISTHu, Lin11-0/+7
2022-11-02Support Intel WRMSRNSHu, Lin11-0/+6
2022-11-02Support Intel CMPccXADDHaochen Jiang1-0/+6
2022-11-02Support Intel AVX-VNNI-INT8Cui,Lili1-0/+11
2022-11-02Support Intel AVX-IFMAHongyu Wang1-0/+7
2022-10-31Support Intel PREFETCHICui, Lili1-0/+7
2022-10-21Support Intel AMX-FP16Cui,Lili1-0/+1
2022-10-20x86: re-work AVX-VNNI supportJan Beulich1-10/+10
2022-09-30x86/Intel: restrict suffix derivationJan Beulich1-155/+145
2022-08-16x86: shorten certain template namesJan Beulich1-26/+32
2022-08-16x86: template-ize certain vector conversion insnsJan Beulich1-97/+44
2022-08-16x86: template-ize vector packed byte/word integer insnsJan Beulich1-145/+74
2022-08-16x86: re-order AVX512 S/G templatesJan Beulich1-28/+25
2022-08-16x86: template-ize vector packed dword/qword integer insnsJan Beulich1-196/+99
2022-08-16x86: template-ize packed/scalar vector floating point insnsJan Beulich1-415/+178
2022-08-16revert "x86: Also pass -P to $(CPP) when processing i386-opc.tbl"Jan Beulich1-22/+27
2022-08-09x86-64: adjust MOVQ to/from SReg attributesJan Beulich1-1/+1
2022-08-09x86: adjust MOVSD attributesJan Beulich1-1/+1
2022-08-09x86: fold AVX VGATHERDPD / VPGATHERDQJan Beulich1-4/+2
2022-08-09x86: allow use of broadcast with X/Y/Z-suffixed AVX512-FP16 insnsJan Beulich1-18/+18
2022-08-09x86/Intel: split certain AVX512-FP16 VCVT*2PH templatesJan Beulich1-6/+12
2022-08-03x86: properly mark i386-only insnsJan Beulich1-9/+9
2022-08-03x86: also use D for MOVBEJan Beulich1-2/+1
2022-08-02x86: XOP shift insns don't really allow B suffixJan Beulich1-4/+4
2022-08-01x86: SKINIT with operand needs IgnoreSizeJan Beulich1-1/+1
2022-07-29x86: drop stray NoRex64 from KeyLocker insnsJan Beulich1-3/+3
2022-07-21x86: replace wrong attributes on VCVTDQ2PH{X,Y}Jan Beulich1-2/+2
2022-07-21x86/Intel: correct AVX512F scatter insn element sizesJan Beulich1-4/+4
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