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path: root/opcodes/i386-opc.h
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2020-08-04x86: Add {disp16} pseudo prefixH.J. Lu1-0/+12
2020-07-02x86: Add SwapSourcesH.J. Lu1-0/+4
2020-06-26x86: Rename VecSIB to SIB for Intel AMXH.J. Lu1-6/+6
2020-06-08x86: restrict use of register aliasesJan Beulich1-1/+1
2020-04-07Add support for intel TSXLDTRK instructions$Cui,Lili1-0/+3
2020-04-02Add support for intel SERIALIZE instructionLiliCui1-0/+3
2020-03-06x86: drop Rex64 attributeJan Beulich1-3/+0
2020-03-04x86: support VMGEXITJan Beulich1-0/+3
2020-03-03x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu1-4/+4
2020-02-17x86: Remove CpuABM and add CpuPOPCNTH.J. Lu1-6/+6
2020-02-11x86: drop ShortForm attributeJan Beulich1-3/+0
2020-02-10x86: Accept Intel64 only instruction by defaultH.J. Lu1-6/+11
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-11-14x86: fold individual Jump* attributes into a single Jump oneJan Beulich1-11/+8
2019-11-14x86: make JumpAbsolute an insn attributeJan Beulich1-3/+3
2019-11-14x86: make AnySize an insn attributeJan Beulich1-5/+4
2019-11-12x86: fold EsSeg into IsStringJan Beulich1-6/+8
2019-11-12x86: eliminate ImmExt abuseJan Beulich1-2/+3
2019-11-12x86: introduce operand type "instance"Jan Beulich1-11/+14
2019-11-08x86: convert RegMask and RegBND from bitfield to enumeratorJan Beulich1-7/+2
2019-11-08x86: convert RegSIMD and RegMMX from bitfield to enumeratorJan Beulich1-6/+2
2019-11-08x86: convert Control/Debug/Test from bitfield to enumeratorJan Beulich1-9/+3
2019-11-08x86: convert SReg from bitfield to enumeratorJan Beulich1-3/+1
2019-11-08x86: introduce operand type "class"Jan Beulich1-4/+13
2019-11-07x86: support further AMD Zen2 instructionsJan Beulich1-0/+6
2019-10-30x86: slightly rearrange struct insn_templateJan Beulich1-4/+4
2019-10-30x86: drop stray WJan Beulich1-1/+3
2019-07-17x86: drop stale Mem enumeratorJan Beulich1-3/+1
2019-07-16x86: make RegMem an opcode modifierJan Beulich1-7/+6
2019-07-16x86: fold SReg{2,3}Jan Beulich1-6/+3
2019-07-01x86: drop Vec_Imm4Jan Beulich1-4/+0
2019-06-04Enable Intel AVX512_VP2INTERSECT insnH.J. Lu1-0/+3
2019-06-04Add support for Intel ENQCMD[S] instructionsH.J. Lu1-0/+3
2019-04-05x86: Support Intel AVX512 BF16Xuepeng Guo1-0/+3
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-10-10x86: fold Size{16,32,64} template attributesJan Beulich1-6/+5
2018-09-14x86: Support VEX/EVEX WIG encodingH.J. Lu1-0/+2
2018-09-13x86: use D attribute also for SIMD templatesJan Beulich1-0/+2
2018-08-11x86: Add CpuCMOV and CpuFXSRH.J. Lu1-0/+6
2018-08-06x86: fold RegEip/RegRip and RegEiz/RegRizJan Beulich1-4/+2
2018-08-03x86: drop "mem" operand type attributeJan Beulich1-1/+0
2018-07-31x86: fold various AVX512 templates with so far differing Masking attributesJan Beulich1-2/+2
2018-07-31x86: drop CpuVREXJan Beulich1-3/+0
2018-07-25x86: Expand Broadcast to 3 bitsH.J. Lu1-1/+12
2018-07-19x86: fold various AVX512VL templates into their AVX512F counterpartsJan Beulich1-1/+2
2018-07-18x86: Split vcvtps2{,u}qq and vcvttps2{,u}qqH.J. Lu1-9/+9
2018-07-11x86: replace off-by-one OTMaxJan Beulich1-4/+4
2018-05-07Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu1-0/+6
2018-05-07x86: Replace AddrPrefixOp0 with AddrPrefixOpRegH.J. Lu1-3/+3
2018-04-27Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist1-24/+0
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