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2024-01-04Update year range in copyright notice of binutils filesAlan Modra1-1/+1
Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out */po/*.pot which we don't update frequently.
2023-09-25Revert "arc: Add new opcode functions for ARCv3 ISA."Claudiu Zissulescu1-6/+0
This reverts commit c99dc76089a2de97ea0ee755aa8e87037a17b6d6.
2023-09-25arc: Add new opcode functions for ARCv3 ISA.Claudiu Zissulescu1-0/+6
opcodes/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> Cupertino Miranda <cmiranda@synopsys.com> * opcodes/Makefile.am: Add ARC64 opcode file. * opcodes/Makefile.in: Regenerate. * opcodes/arc-opc.c: Move the common functionality to arcxx-opc.inc. Keep only ARCv2 ARCv1 specifics. * opcodes/arc-ext-tbl.h: Deleted file. * opcodes/arcxx-opc.inc: New file. * opcodes/arc64-opc.c: Likewise. * opcodes/arc-fxi.h (insert_uimm9_a32_11_s): New function. (extract_uimm9_a32_11_s): Likewise. (insert_uimm10_13_s): Likewise. (extract_uimm10_13_s): Likewise. * opcodes/configure: Regenerate. * opcodes/configure.ac: Add ARC64 target. * opcodes/disassemble.c: Likewise. * opcodes/arc-dis.c (regmod_t): New type. (regmods): New structure. (fpnames): New strings with fp-regs name. (REG_PCL, REG_LIMM, REG_LIMM_S, REG_U32, REG_S32): New defines. (getregname): New function. (find_format_from_table): Discriminate between signed and unsigned 32bit immediates. (find_format): Handle extract function for flags. (arc_insn_length): Update insn lengths to various architectures. (print_insn_arc): Update printing for various ARC architectures. * opcodes/arc-flag-classes.def: New file. * opcodes/arc-flag.def: New file. * opcodes/arc-operands.def: New file. * opcodes/arc-regs.h: Changed. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2023-08-16kvx: New port.Paul Iannetta1-0/+9
2023-08-02Revert "2.41 Release sources"Sam James1-39/+5
This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton1-5/+39
2023-07-30bpf: include, bfd, opcodes: add EF_BPF_CPUVER ELF header flagsJose E. Marchesi1-20/+0
This patch adds support for EF_BPF_CPUVER bits in the ELF machine-dependent header flags. These bits encode the BPF CPU version for which the object file has been compiled for. The BPF assembler is updated so it annotates the object files it generates with these bits. The BPF disassembler is updated so it honors EF_BPF_CPUVER to use the appropriate ISA version if the user didn't specify an explicit ISA version in the command line. Note that a value of zero in EF_BPF_CPUVER is interpreted by the disassembler as "use the later supported version" (the BPF CPU versions start with v1.) The readelf utility is updated to pretty print EF_BPF_CPUVER when it prints out the ELF header: $ readelf -h a.out ELF Header: ... Flags: 0x4, CPU Version: 4 Tested in bpf-unknown-none. include/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * elf/bpf.h (EF_BPF_CPUVER): Define. * opcode/bpf.h (BPF_XBPF): Change from 0xf to 0xff so it fits in EF_BPF_CPUVER. binutils/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * readelf.c (get_machine_flags): Recognize and pretty print BPF machine flags. opcodes/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-dis.c: Initialize asm_bpf_version to -1. (print_insn_bpf): Set BPF ISA version from the cpu version ELF header flags if no explicit version set in the command line. * disassemble.c (disassemble_init_for_target): Remove unused code. gas/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.h (elf_tc_final_processing): Define. * config/tc-bpf.c (bpf_elf_final_processing): New function.
2023-07-21DesCGENization of the BPF binutils portJose E. Marchesi1-22/+8
CGEN is cool, but the BPF architecture is simply too bizarre for it. The weird way of BPF to handle endianness in instruction encoding, the weird C-like alternative assembly syntax, the weird abuse of multi-byte (or infra-byte) instruction fields as opcodes, the unusual presence of opcodes beyond the first 32-bits of some instructions, are all examples of what makes it a PITA to continue using CGEN for this port. The bpf.cpu file is becoming so complex and so nested with p-macros that it is very difficult to read, and quite challenging to update. Also, every time we are forced to change something in CGEN to accommodate BPF requirements (which is often) we have to do extensive testing to make sure we do not break any other target using CGEN. This is getting un-maintenable. So I have decided to bite the bullet and revamp/rewrite the port so it no longer uses CGEN. Overall, this involved: * To remove the cpu/bpf.{cpu,opc} descriptions. * To remove the CGEN generated files. * To replace the CGEN generated opcodes table with a new hand-written opcodes table for BPF. * To replace the CGEN generated disassembler wih a new disassembler that uses the new opcodes. * To replace the CGEN generated assembler with a new assembler that uses the new opcodes. * To replace the CGEN generated simulator with a new simulator that uses the new opcodes. [This is pushed in GDB in another patch.] * To adapt the build systems to the new situation. Additionally, this patch introduces some extensions and improvements: * A new BPF relocation BPF_RELOC_BPF_DISP16 plus corresponding ELF relocation R_BPF_GNU_64_16 are added to the BPF BFD port. These relocations are used for section-relative 16-bit offsets used in load/store instructions. * The disassembler now has support for the "pseudo-c" assembly syntax of BPF. What dialect to use when disassembling is controlled by a command line option. * The disassembler now has support for dumping instruction immediates in either octal, hexadecimal or decimal. The used output base is controlled by a new command-line option. * The GAS BPF test suite has been re-structured and expanded in order to test the disassembler pseudoc syntax support. Minor bugs have been also fixed there. The assembler generic tests that were disabled for bpf-*-* targets due to the previous implementation of pseudoc syntax are now re-enabled. Additional tests have been added to test the new features of the assembler. .dump files are no longer used. * The linker BPF test suite has been adapted to the command line options used by the new disassembler. The result is very satisfactory. This patchs adds 3448 lines of code and removes 10542 lines of code. Tested in: * Target bpf-unknown-none with 64-bit little-endian host and 32-bit little-endian host. * Target x86-64-linux-gnu with --enable-targets=all Note that I have not tested in a big-endian host yet. I will do so once this lands upstream so I can use the GCC compiler farm. I have not included ChangeLog entries in this patch: these would be massive and not very useful, considering this is pretty much a rewrite of the port. I beg the indulgence of the global maintainers.
2023-06-30opcodes/loongarch: implement style support in the disassemblerWANG Xuerui1-0/+5
Update the LoongArch disassembler to supply style information to the disassembler output. The output formatting remains unchanged. opcodes/ChangeLog: * disassemble.c: Mark LoongArch as created_styled_output=true. * loongarch-dis.c (dis_one_arg): Use fprintf_styled_func throughout with proper styles. Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-05-19RISC-V: Minor improvements for dis-assembler.Nelson Chu1-0/+1
* Extract all private_data initializations into riscv_init_disasm_info, which called from print_insn_riscv rather than riscv_disassemble_insn. * The disassemble_free_target seems like the right place to release all target private_data, also including the internal data structures, like riscv_subsets. Therefore, add a new function, disassemble_free_riscv, to release them for safe. opcodes/ * disassemble.c (disassemble_free_target): Called disassemble_free_riscv for riscv to release private_data and internal data structures. * disassemble.h: Added extern disassemble_free_riscv. * riscv-dis.c (riscv_init_disasm_info): New function, used to init riscv_private_data. (riscv_disassemble_insn): Moved riscv_private_data initializations into riscv_init_disasm_info. (print_insn_riscv): Called riscv_init_disasm_info to init riscv_private_data once time. (disassemble_free_riscv): New function, used to free the internal data structures, like riscv_subsets.
2023-02-25opcodes/m68k: enable libopcodes styling for GDBAndrew Burgess1-0/+5
The following commit added libopcodes styling for m68k: commit c22ff449275c91e4842bb10c650e83c572580f65 Date: Tue Feb 14 18:07:19 2023 +0100 opcodes: style m68k disassembler output but didn't set disassemble_info::created_styled_output in disassemble.c, which is needed in order for GDB to start using the libopcodes based styling. This commit fixes this small oversight. GDB now styles correctly.
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
2022-12-05libopcodes/mips: add support for disassembler stylingAndrew Burgess1-0/+5
This commit adds disassembler styling support for MIPS. After this commit objdump and GDB will style disassembler output. This is a pretty straight forward change, we switch to use the disassemble_info::fprintf_styled_func callback, and pass an appropriate style through as needed. No additional tricks were needed (compared to say i386, or ARM). Tested by running all of the objdump commands used by the gas testsuite and manually inspecting the styled output, everything looks reasonable, though I'm not a MIPS expert, so it is possible that I've missed some corner cases. Worst case though is that something will be styled incorrectly, the actual content should be unchanged. All the gas, ld, and binutils tests still pass for me.
2022-11-01opcodes/arm: add disassembler styling for armAndrew Burgess1-0/+1
This commit adds disassembler styling for the ARM architecture. The ARM disassembler is driven by several instruction tables, e.g. cde_opcodes, coprocessor_opcodes, neon_opcodes, etc The type for elements in each table can vary, but they all have one thing in common, a 'const char *assembler' field. This field contains a string that describes the assembler syntax of the instruction. Embedded within that assembler syntax are various escape characters, prefixed with a '%'. Here's an example of a very simple instruction from the arm_opcodes table: "pld\t%a" The '%a' indicates a particular type of operand, the function print_insn_arm processes the arm_opcodes table, and includes a switch statement that handles the '%a' operand, and takes care of printing the correct value for that instruction operand. It is worth noting that there are many print_* functions, each function handles a single *_opcodes table, and includes its own switch statement for operand handling. As a result, every *_opcodes table uses a different mapping for the operand escape sequences. This means that '%a' might print an address for one *_opcodes table, but in a different *_opcodes table '%a' might print a register operand. Notice as well that in our example above, the instruction mnemonic 'pld' is embedded within the assembler string. Some instructions also include comments within the assembler string, for example, also from the arm_opcodes table: "nop\t\t\t@ (mov r0, r0)" here, everything after the '@' is a comment that is displayed at the end of the instruction disassembly. The next complexity is that the meaning of some escape sequences is not necessarily fixed. Consider these two examples from arm_opcodes: "ldrex%c\tr%12-15d, [%16-19R]" "setpan\t#%9-9d" Here, the '%d' escape is used with a bitfield modifier, '%12-15d' in the first instruction, and '%9-9d' in the second instruction, but, both of these are the '%d' escape. However, in the first instruction, the '%d' is used to print a register number, notice the 'r' immediately before the '%d'. In the second instruction the '%d' is used to print an immediate, notice the '#' just before the '%d'. We have two problems here, first, the '%d' needs to know if it should use register style or immediate style, and secondly, the 'r' and '#' characters also need to be styled appropriately. The final thing we must consider is that some escape codes result in more than just a single operand being printed, for example, the '%q' operand as used in arm_opcodes ends up calling arm_decode_shift, which can print a register name, a shift type, and a shift amount, this could end up using register, sub-mnemonic, and immediate styles, as well as the text style for things like ',' between the different parts. I propose a three layer approach to adding styling: (1) Basic state machine: When we start printing an instruction we should maintain the idea of a 'base_style'. Every character from the assembler string will be printed using the base_style. The base_style will start as mnemonic, as each instruction starts with an instruction mnemonic. When we encounter the first '\t' character, the base_style will change to text. When we encounter the first '@' the base_style will change to comment_start. This simple state machine ensures that for simple instructions the basic parts, except for the operands themselves, will be printed in the correct style. (2) Simple operand styling: For operands that only have a single meaning, or which expand to multiple parts, all of which have a consistent meaning, then I will simply update the operand printing code to print the operand with the correct style. This will cover a large number of the operands, and is the most consistent with how styling has been added to previous architectures. (3) New styling syntax in assembler strings: For cases like the '%d' that I describe above, I propose adding a new extension to the assembler syntax. This extension will allow me to temporarily change the base_style. Operands like '%d', will then print using the base_style rather than using a fixed style. Here are the two examples from above that use '%d', updated with the new syntax extension: "ldrex%c\t%{R:r%12-15d%}, [%16-19R]" "setpan\t%{I:#%9-9d%}" The syntax has the general form '%{X:....%}' where the 'X' character changes to indicate a different style. In the first instruction I use '%{R:...%}' to change base_style to the register style, and in the second '%{I:...%}' changes base_style to immediate style. Notice that the 'r' and '#' characters are included within the new style group, this ensures that these characters are printed with the correct style rather than as text. The function decode_base_style maps from character to style. I've included a character for each style for completeness, though only a small number of styles are currently used. I have updated arm-dis.c to the above scheme, and checked all of the tests in gas/testsuite/gas/arm/, and the styling looks reasonable. There are no regressions on the ARM gas/binutils/ld tests that I can see, so I don't believe I've changed the output layout at all. There were two binutils tests for which I needed to force the disassembler styling off. I can't guarantee that I've not missed some untested corners of the disassembler, or that I might have just missed some incorrectly styled output when reviewing the test results, but I don't believe I've introduced any changes that could break the disassembler - the worst should be some aspect is not styled correctly.
2022-07-29libopcodes/aarch64: add support for disassembler stylingAndrew Burgess1-0/+1
This commit enables disassembler styling for AArch64. After this commit it is possible to have objdump style AArch64 disassembler output (using --disassembler-color option). Once the required GDB patches are merged, GDB will also style the disassembler output. The changes to support styling are mostly split between two files opcodes/aarch64-dis.c and opcodes/aarch64-opc.c. The entry point for the AArch64 disassembler can be found in aarch64-dis.c, this file handles printing the instruction mnemonics, and assembler directives (e.g. '.byte', '.word', etc). Some operands, mostly relating to assembler directives are also printed from this file. This commit changes all of this to pass through suitable styling information. However, for most "normal" instructions, the instruction operands are printed using a two step process. From aarch64-dis.c, in the print_operands function, the function aarch64_print_operand is called, this function is in aarch64-opc.c, and converts an instruction operand into a string. Then, back in print_operands (aarch64-dis.c), the operand string is printed. Unfortunately, the string returned by aarch64_print_operand can be quite complex, it will include syntax elements, like '[' and ']', in addition to register names and immediate values. In some cases, a single operand will expand into what will appear (to the user) as multiple operands separated with a ','. This makes the task of styling more complex, all these different components need to by styled differently, so we need to get the styling information out of aarch64_print_operand in some way. The solution that I propose here is similar to the solution that I used for the i386 disassembler. Currently, aarch64_print_operand uses snprintf to write the operand text into a buffer provided by the caller. What I propose is that we pass an extra argument to the aarch64_print_operand function, this argument will be a structure, the structure contains a callback function and some state. When aarch64_print_operand needs to format part of its output this can be done by using the callback function within the new structure, this callback returns a string with special embedded markers that indicate which mode should be used for each piece of text. Back in aarch64-dis.c we can spot these special style markers and use this to split the disassembler output up and apply the correct style to each piece. To make aarch64-opc.c clearer a series of new static functions have been added, e.g. 'style_reg', 'style_imm', etc. Each of these functions formats a piece of text in a different style, 'register' and 'immediate' in this case. Here's an example taken from aarch64-opc.c of the new functions in use: snprintf (buf, size, "[%s, %s]!", style_reg (styler, base), style_imm (styler, "#%d", opnd->addr.offset.imm)); The aarch64_print_operand function is also called from the assembler to aid in printing diagnostic messages. Right now I have no plans to add styling to the assembler output, and so, the callback function used in the assembler ignores the styling information and just returns an plain string. I've used the source files in gas/testsuite/gas/aarch64/ for testing, and have manually gone through and checked that the styling looks reasonable, however, I'm not an AArch64 expert, so it is possible that the odd piece is styled incorrectly. Please point out any mistakes I've made. With objdump disassembler color turned off, there should be no change in the output after this commit.
2022-07-25libopcodes/ppc: add support for disassembler stylingAndrew Burgess1-0/+1
This commit adds disassembler styling to the libopcodes ppc disassembler. This conversion was pretty straight forward, I just converted the fprintf_func calls to fprintf_styled_func calls and added an appropriate style. For testing the new styling I just assembled then disassembled the source files in gas/testsuite/gas/ppc and manually checked that the styling looked reasonable. I think the only slightly weird case was how things like '4*cr1+eq' are styled. As best I can tell, this construct, used for example in this instruction: crand 4*cr1+lt,4*cr1+gt,4*cr1+eq is used to access a field of a control register. I initially tried styling this whole construct as a register[1], but during review it was suggested that instead different parts of the text should have different styles. In this commit I propose styling '4*cr1+lt' like this: 4 - immediate, * - text, cr1 - register + - text lt - sub-mnemonic If the user does not request styled output from objdump, then there should be no change in the disassembler output after this commit. [1] https://sourceware.org/pipermail/binutils/2022-July/121771.html
2022-07-18opcodes/arc: Implement style support in the disassemblerClaudiu Zissulescu1-0/+5
Update the ARC disassembler to supply style information to the disassembler output. The output formatting remains unchanged. opcodes/ChangeLog: * disassemble.c (disassemble_init_for_target): Set created_styled_output for ARC based targets. * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype instead of fprintf_ftype throughout. (find_format): Likewise. (print_flags): Likewise. (print_insn_arc): Likewise. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2022-07-08libopcodes/s390: add support for disassembler stylingAndrew Burgess1-0/+1
This commit adds disassembler style to the libopcodes s390 disassembler. This conversion was pretty straight forward, I just converted the fprintf_func calls to fprintf_styled_func calls and added an appropriate style. For testing the new styling I just assembled then disassembled the source files in gas/testsuite/gas/s390 and manually checked that the styling looked reasonable. If the user does not request styled output from objdump, then there should be no change in the disassembler output after this commit.
2022-07-04opcodes/avr: Implement style support in the disassemblerMarcus Nilsson1-0/+5
* disassemble.c: (disassemble_init_for_target): Set created_styled_output for AVR based targets. * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype instead of fprintf_ftype throughout. (avr_operand): Pass in and fill disassembler_style when parsing operands.
2022-06-27drop XC16x bitsJan Beulich1-6/+0
Commit 04f096fb9e25 ("Move the xc16x target to the obsolete list") moved the architecture from the "obsolete but still available" to the "obsolete / support removed" list in config.bfd, making the architecture impossible to enable (except maybe via "enable everything" options"). Note that I didn't touch */po/*.po{,t} on the assumption that these would be updated by some (half)automatic means.
2022-05-05Don't define ARCH_cris for BFD64Luis Machado1-1/+1
I believe it is a mistake to define ARCH_cris when BFD64 is defined. It is a 32-bit architecture, so should be placed outside of the BFD64 block.
2022-04-04opcodes/i386: partially implement disassembler style supportAndrew Burgess1-1/+6
This commit adds partial support for disassembler styling in the i386 disassembler. The i386 disassembler collects the instruction arguments into an array of strings, and then loops over the array printing the arguments out later on. The problem is that by the time we print the arguments out it's not obvious what the type of each argument is. Obviously this can be fixed, but I'd like to not do that as part of this commit, rather, I'd prefer to keep this commit as small as possible to get the basic infrastructure in place, then we can improve on this, to add additional styling, in later commits. For now then, I think this commit should correctly style mnemonics, some immediates, and comments. Everything else will be printed as plain text, which will include most instruction arguments, unless the argument is printed as a symbol, by calling the print_address_func callback. Ignoring colours, there should be no other user visible changes in the output of the disassembler in either objdump or gdb. opcodes/ChangeLog: * disassembler.c (disassemble_init_for_target): Set created_styled_output for i386 based targets. * i386-dis.c: Changed throughout to use fprintf_styled_func instead of fprintf_func.
2022-04-04opcodes/riscv: implement style support in the disassemblerAndrew Burgess1-0/+1
Update the RISC-V disassembler to supply style information. This allows objdump to apply syntax highlighting to the disassembler output (when the appropriate command line flag is used). Ignoring colours, there should be no other user visible changes in the output of the disassembler in either objdump or gdb. opcodes/ChangeLog: * disassembler.c (disassemble_init_for_target): Set created_styled_output for riscv. * riscv-dis.c: Changed throughout to use fprintf_styled_func instead of fprintf_func.
2022-04-04objdump/opcodes: add syntax highlighting to disassembler outputAndrew Burgess1-0/+13
This commit adds the _option_ of having disassembler output syntax highlighted in objdump. This option is _off_ by default. The new command line options are: --disassembler-color=off # The default. --disassembler-color=color --disassembler-color=extended-color I have implemented two colour modes, using the same option names as we use of --visualize-jumps, a basic 8-color mode ("color"), and an extended 8bit color mode ("extended-color"). The syntax highlighting requires that each targets disassembler be updated; each time the disassembler produces some output we now pass through an additional parameter indicating what style should be applied to the text. As updating all target disassemblers is a large task, the old API is maintained. And so, a user of the disassembler (i.e. objdump, gdb) must provide two functions, the current non-styled print function, and a new, styled print function. I don't currently have a plan for converting every single target disassembler, my hope is that interested folk will update the disassemblers they are interested in. But it is possible some might never get updated. In this initial series I intend to convert the RISC-V disassembler completely, and also do a partial conversion of the x86 disassembler. Hopefully having the x86 disassembler at least partial converted will allow more people to try this out easily and provide feedback. In this commit I have focused on objdump. The changes to GDB at this point are the bare minimum required to get things compiling, GDB makes no use of the styling information to provide any colors, that will come later, if this commit is accepted. This first commit in the series doesn't convert any target disassemblers at all (the next two commits will update some targets), so after this commit, the only color you will see in the disassembler output, is that produced from objdump itself, e.g. from objdump_print_addr_with_sym, where we print an address and a symbol name, these are now printed with styling information, and so will have colors applied (if the option is on). Finally, my ability to pick "good" colors is ... well, terrible. I'm in no way committed to the colors I've picked here, so I encourage people to suggest new colors, or wait for this commit to land, and then patch the choice of colors. I do have an idea about using possibly an environment variable to allow the objdump colors to be customised, but I haven't done anything like that in this commit, the color choices are just fixed in the code for now. binutils/ChangeLog: * NEWS: Mention new feature. * doc/binutils.texi (objdump): Describe --disassembler-color option. * objdump.c (disassembler_color): New global. (disassembler_extended_color): Likewise. (disassembler_in_comment): Likewise. (usage): Mention --disassembler-color option. (long_options): Add --disassembler-color option. (objdump_print_value): Use fprintf_styled_func instead of fprintf_func. (objdump_print_symname): Likewise. (objdump_print_addr_with_sym): Likewise. (objdump_color_for_disassembler_style): New function. (objdump_styled_sprintf): New function. (fprintf_styled): New function. (disassemble_jumps): Use disassemble_set_printf, and reset disassembler_in_comment. (null_styled_print): New function. (disassemble_bytes): Use disassemble_set_printf, and reset disassembler_in_comment. (disassemble_data): Update init_disassemble_info call. (main): Handle --disassembler-color option. include/ChangeLog: * dis-asm.h (enum disassembler_style): New enum. (struct disassemble_info): Add fprintf_styled_func field, and created_styled_output field. (disassemble_set_printf): Declare. (init_disassemble_info): Add additional parameter. (INIT_DISASSEMBLE_INFO): Add additional parameter. opcodes/ChangeLog: * dis-init.c (init_disassemble_info): Take extra parameter, initialize the new fprintf_styled_func and created_styled_output fields. * disassembler.c (disassemble_set_printf): New function definition.
2022-03-31x86: Remove bfd_arch_l1om and bfd_arch_k1omH.J. Lu1-2/+0
Remove bfd_arch_l1om and bfd_arch_k1om since L1OM/K1OM support has been removed from gas, ld and opcodes. bfd/ * Makefile.am (ALL_MACHINES): Remove cpu-l1om.lo and cpu-k1om.lo. (ALL_MACHINES_CFILES): Remove cpu-l1om.c and cpu-k1om.c. * archures.c (bfd_mach_l1om): Removed. (bfd_mach_l1om_intel_syntax): Likewise. (bfd_mach_k1om): Likewise. (bfd_mach_k1om_intel_syntax): Likewise. (bfd_k1om_arch): Likewise. (bfd_l1om_arch): Likewise. (bfd_archures_list): Remove bfd_k1om_arch and bfd_l1om_arch references. * config.bfd (targ_selvecs): Remove l1om_elf64_vec. l1om_elf64_fbsd_vec, k1om_elf64_vec and k1om_elf64_fbsd_vec. (targ_archs): Remove bfd_l1om_arch and bfd_k1om_arch. * configure.ac (k1om_elf64_vec): Removed. (k1om_elf64_fbsd_vec): Likewise. (l1om_elf64_vec): Likewise. (l1om_elf64_fbsd_vec): Likewise. * cpu-k1om.c: Removed. * cpu-l1om.c: Likewise. * elf64-x86-64.c (elf64_l1om_elf_object_p): Removed. (elf64_k1om_elf_object_p): Likewise. (l1om_elf64_vec): Removed. (l1om_elf64_fbsd_vec): Likewise. (k1om_elf64_vec): Likewise. (k1om_elf64_fbsd_vec): Likewise. (ELF_TARGET_OS): Undefine. * targets.c (_bfd_target_vector): Remove k1om_elf64_vec, k1om_elf64_fbsd_vec, l1om_elf64_vec and l1om_elf64_fbsd_vec. * Makefile.in: Regenerate. * bfd-in2.h: Likewise. * configure: Likewise. opcodes/ * configure.ac: Remove bfd_arch_l1om/bfd_arch_k1om references. * disassemble.c (disassembler): Likewise. * configure: Regenerate.
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out */po/*.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.
2021-11-12Don't compile some opcodes files when bfd is 32-bit onlyAlan Modra1-10/+12
* Makefile.am (TARGET_LIBOPCODES_CFILES): Split into.. (TARGET64_LIBOPCODES_CFILES): ..this and.. (TARGET32_LIBOPCODES_CFILES): ..this. (ALL_MACHINES): Likewise split to (ALL64_MACHINES, ALL32_MACHINES): ..this. * disassemble.c: Define some ARCH_* when ARCH_all only if BFD64. * configure.ac (BFD_MACHINES): Defined depending on BFD_ARCH_SIZE. * Makefile.in: Regenerate. * configure: Regenerate.
2021-10-24LoongArch opcodes supportliuzhensong1-0/+9
2021-10-22 Chenghua Xu <xuchenghua@loongson.cn> Zhensong Liu <liuzhensong@loongson.cn> Weinan Liu <liuweinan@loongson.cn> include/ * opcode/loongarch.h: New. * dis-asm.h: Declare print_loongarch_disassembler_options. opcodes/ * Makefile.am: Add LoongArch. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Declare print_insn_loongarch. * loongarch-coder.c: New. * loongarch-dis.c: New. * loongarch-opc.c: New. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
2021-03-31Use bool in opcodesAlan Modra1-6/+6
cpu/ * frv.opc: Replace bfd_boolean with bool, FALSE with false, and TRUE with true throughout. opcodes/ * sysdep.h (POISON_BFD_BOOLEAN): Define. * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h, * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h, * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c, * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c, * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c, * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c, * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c, * microblaze-dis.h, * micromips-opc.c, * mips-dis.c, * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c, * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c, * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c, * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c, * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false, and TRUE with true throughout.
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-12-10RISC-V: Dump CSR according to the elf privileged spec attributes.Nelson Chu1-1/+1
opcodes/ * disassemble.h (riscv_get_disassembler): Declare. * disassemble.c (disassembler): Changed to riscv_get_disassembler. * riscv-dis.c (riscv_get_disassembler): Check the elf privileged spec attributes before calling print_insn_riscv. (parse_riscv_dis_option): Same as the assembler, the priority of elf attributes are higher than the options. If we find the privileged attributes, but the -Mpriv-spec= is different, then output error/warning and still use the elf attributes set.
2020-08-26opcodes: Add missing entries to ebpf_isa_attrJose E. Marchesi1-1/+1
opcodes/ * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
2020-08-26bpf: add xBPF ISADavid Faust1-3/+11
This patch adds support for xBPF, another ISA targetting the BPF virtual architecture. For now, the primary difference between eBPF and xBPF is that xBPF supports indirect calls through the 'call %reg' form of the call instruction. bfd/ * archures.c (bfd_mach_xbpf): Define. * bfd-in2.h: Regenerate. * cpu-bpf.c (bfd_xbpf_arch) New. (bfd_bpf_arch) Update next in list field to point to xbpf arch. cpu/ * bpf.cpu (arch bpf): Add xbpf mach and isas. (define-xbpf-isa) New pmacro. (all-isas) Add xbpfle,xbpfbe. (endian-isas): New pmacro. (mach xbpf): New. (model xbpf-def): Likewise. (h-gpr): Add xbpf mach. (f-dstle, f-srcle, dstle, srcle): Add xbpfle isa. (f-dstbe, f-srcbe, dstbe, srcbe): Add xbpfbe isa. (define-alu-insn-un): Use new endian-isas pmacro. (define-alu-insn-bin, define-alu-insn-mov): Likewise. (define-endian-insn, define-lddw): Likewise. (dlind, dxli, dxsi, dsti): Likewise. (define-cond-jump-insn, define-call-insn): Likewise. (define-atomic-insns): Likewise. gas/ * config/tc-bpf.c: Add option -mxbpf to select xbpf isa. * testsuite/gas/bpf/indcall-1.d: New file. * testsuite/gas/bpf/indcall-1.s: Likewise. * testsuite/gas/bpf/indcall-bad-1.l: Likewise. * testsuite/gas/bpf/indcall-bad-1.s: Likewise. * testsuite/gas/bpf/bpf.exp: Run new tests. opcodes/ * bpf-desc.c: Regenerate. * bpf-desc.h: Likewise. * bpf-opc.c: Likewise. * bpf-opc.h: Likewise. * disassemble.c (disassemble_init_for_target): Set bits for xBPF ISA when appropriate.
2020-06-04cpu,gas,opcodes: remove no longer needed workaround from the BPF portJose E. Marchesi1-0/+1
cpu/ChangeLog: 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64. * bpf.opc (bpf_print_insn): Do not set endian_code here. gas/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to bpf_cgen_cpu_open. (md_assemble): Remove no longer needed hack. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * disassemble.c (disassemble_init_for_target): Set endian_code for bpf targets. * bpf-desc.c: Regenerate. * bpf-opc.c: Likewise. * bpf-dis.c: Likewise.
2020-03-26Re: H8300 use of uninitialised valueAlan Modra1-1/+9
This patch also had some problems. Calculation of maxlen was wrong, and the insn arg loop needed rearranging to work with a correct length. * disassemble.h (opcodes_assert): Declare. (OPCODES_ASSERT): Define. * disassemble.c: Don't include assert.h. Include opintl.h. (opcodes_assert): New function. * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT. (bfd_h8_disassemble): Reduce size of data array. Correctly calculate maxlen. Omit insn decoding when insn length exceeds maxlen. Exit from nibble loop when looking for E, before accessing next data byte. Move processing of E outside loop. Replace tests of maxlen in loop with assertions.
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-12-17Remove tic80 supportAlan Modra1-6/+0
This is one way of fixing ubsan bug reports, just delete the code. The assembler support was removed back in 2005 along with other non-BFD assemblers, but somehow the remainder of the port stayed in. bfd/ * coff-tic80.c: Delete file. * cpu-tic80.c: Delete file. * archures.c: Remove tic80 support. * coffcode.h: Likewise. * coffswap.h: Likewise. * targets.c: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * Makefile.am: Likewise. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. binutils/ * testsuite/binutils-all/objcopy.exp: Remove tic80 support. * testsuite/binutils-all/objdump.exp: Likewise. gas/ * doc/as.texi: Remove mention of tic80. include/ * coff/tic80.h: Delete file. * opcode/tic80.h: Delete file. ld/ * emulparams/tic80coff.sh: Delete file. * scripttempl/tic80coff.sc: Delete file. * configure.tgt: Remove tic80 support. * Makefile.am: Likewise. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate. opcodes/ * tic80-dis.c: Delete file. * tic80-opc.c: Delete file. * disassemble.c: Remove tic80 support. * disassemble.h: Likewise. * Makefile.am: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
2019-12-10PR24960, Memory leak from disassemblerAlan Modra1-0/+59
PR 24960 include/ * dis-asm.h (disassemble_free_target): Declare. opcodes/ * disassemble.c (disassemble_free_target): New function. binutils/ * objdump.c (disassemble_data): Call disassemble_free_target.
2019-12-10Use disassemble_info.private_data in place of insn_setsAlan Modra1-12/+12
No cgen target uses private_data. This patch removes a disassemble_info field that is only used by cgen, and instead uses private_data. It also removes a macro that is no longer used. include/ * dis-asm.h (struct disassemble_info): Delete insn_sets. (INIT_DISASSEMBLE_INFO_NO_ARCH): Don't define. opcodes/ * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data. * disassemble.c (disassemble_init_for_target): Likewise. * bpf-dis.c: Regenerate. * epiphany-dis.c: Regenerate. * fr30-dis.c: Regenerate. * frv-dis.c: Regenerate. * ip2k-dis.c: Regenerate. * iq2000-dis.c: Regenerate. * lm32-dis.c: Regenerate. * m32c-dis.c: Regenerate. * m32r-dis.c: Regenerate. * mep-dis.c: Regenerate. * mt-dis.c: Regenerate. * or1k-dis.c: Regenerate. * xc16x-dis.c: Regenerate. * xstormy16-dis.c: Regenerate.
2019-05-23opcodes: add support for eBPFJose E. Marchesi1-0/+35
This patch adds support for the Linux kernel eBPF architecture to the opcodes. The port is based on CGEN. opcodes/ChangeLog: 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com> * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch. * configure: Regenerated. * Makefile.am: Add rules for the files generated from cpu/bpf.cpu and cpu/bpf.opc. (HFILES): Add bpf-desc.h and bpf-opc.h. (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c, bpf-ibld.c and bpf-opc.c. (BPF_DEPS): Define. * Makefile.in: Regenerated. * disassemble.c (ARCH_bpf): Define. (disassembler): Add case for bfd_arch_bpf. (disassemble_init_for_target): Likewise. (enum epbf_isa_attr): Define. * disassemble.h: extern print_insn_bpf. * bpf-asm.c: Generated. * bpf-opc.h: Likewise. * bpf-opc.c: Likewise. * bpf-ibld.c: Likewise. * bpf-dis.c: Likewise. * bpf-desc.h: Likewise. * bpf-desc.c: Likewise.
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-12-06opcodes/riscv: Hide '.L0 ' fake symbolsAndrew Burgess1-0/+5
The RISC-V assembler generates fake labels with the name '.L0 ' as part of the debug information (see gas/config/tc-riscv.h:FAKE_LABEL_NAME). The problem is that currently, when disassembling an object file, the output looks like this (this is an example from the GDB testsuite, but is pretty representative of anything with debug information): 000000000000001e <main>: 1e: 7179 addi sp,sp,-48 20: f406 sd ra,40(sp) 22: f022 sd s0,32(sp) 24: 1800 addi s0,sp,48 0000000000000026 <.L0 >: 26: 87aa mv a5,a0 28: feb43023 sd a1,-32(s0) 2c: fcc43c23 sd a2,-40(s0) 30: fef42623 sw a5,-20(s0) 0000000000000034 <.L0 >: 34: fec42783 lw a5,-20(s0) 38: 0007871b sext.w a4,a5 3c: 678d lui a5,0x3 3e: 03978793 addi a5,a5,57 # 3039 <.LASF30+0x2a9d> 42: 02f71463 bne a4,a5,6a <.L0 > 0000000000000046 <.L0 >: 46: 000007b7 lui a5,0x0 4a: 0007b783 ld a5,0(a5) # 0 <need_malloc> 4e: 6f9c ld a5,24(a5) 0000000000000050 <.L0 >: 50: 86be mv a3,a5 52: 466d li a2,27 54: 4585 li a1,1 56: 000007b7 lui a5,0x0 5a: 00078513 mv a0,a5 5e: 00000097 auipc ra,0x0 62: 000080e7 jalr ra # 5e <.L0 +0xe> 0000000000000066 <.L0 >: 66: 4785 li a5,1 68: a869 j 102 <.L0 > 000000000000006a <.L0 >: 6a: 000007b7 lui a5,0x0 6e: 00078513 mv a0,a5 72: 00000097 auipc ra,0x0 76: 000080e7 jalr ra # 72 <.L0 +0x8> The frequent repeated '.L0 ' labels are pointless, as they are non-unique there's no way to match a use of '.L0 ' to its appearence in the output, so we'd be better off just not printing it at all. That's what this patch does by defining a 'symbol_is_valid' method for RISC-V. With this commit, the same disassembly now looks like this: 000000000000001e <main>: 1e: 7179 addi sp,sp,-48 20: f406 sd ra,40(sp) 22: f022 sd s0,32(sp) 24: 1800 addi s0,sp,48 26: 87aa mv a5,a0 28: feb43023 sd a1,-32(s0) 2c: fcc43c23 sd a2,-40(s0) 30: fef42623 sw a5,-20(s0) 34: fec42783 lw a5,-20(s0) 38: 0007871b sext.w a4,a5 3c: 678d lui a5,0x3 3e: 03978793 addi a5,a5,57 # 3039 <.LASF30+0x2a9d> 42: 02f71463 bne a4,a5,6a <.L4> 46: 000007b7 lui a5,0x0 4a: 0007b783 ld a5,0(a5) # 0 <need_malloc> 4e: 6f9c ld a5,24(a5) 50: 86be mv a3,a5 52: 466d li a2,27 54: 4585 li a1,1 56: 000007b7 lui a5,0x0 5a: 00078513 mv a0,a5 5e: 00000097 auipc ra,0x0 62: 000080e7 jalr ra # 5e <main+0x40> 66: 4785 li a5,1 68: a869 j 102 <.L5> 000000000000006a <.L4>: 6a: 000007b7 lui a5,0x0 6e: 00078513 mv a0,a5 72: 00000097 auipc ra,0x0 76: 000080e7 jalr ra # 72 <.L4+0x8> In order to share the fake label between the assembler and the libopcodes library, I've added some new defines RISCV_FAKE_LABEL_NAME and RISCV_FAKE_LABEL_CHAR in include/opcode/riscv.h. I could have just moved FAKE_LABEL_NAME to the include file, however, I thnk this would be confusing, someone working on the assembler would likely not expect to find FAKE_LABEL_NAME defined outside of the assembler source tree. By introducing the RISCV_FAKE_LABEL_* defines I can leave the assembler standard FAKE_LABEL_ defines in the assembler source, but still share the RISCV_FAKE_LABEL_* with libopcodes. gas/ChangeLog: * config/tc-riscv.h (FAKE_LABEL_NAME): Define as RISCV_FAKE_LABEL_NAME. (FAKE_LABEL_CHAR): Define as RISCV_FAKE_LABEL_CHAR. include/ChangeLog: * dis-asm.h (riscv_symbol_is_valid): Declare. * opcode/riscv.h (RISCV_FAKE_LABEL_NAME): Define. (RISCV_FAKE_LABEL_CHAR): Define. opcodes/ChangeLog: * disassembler.c (disassemble_init_for_target): Add RISC-V initialisation. * riscv-dis.c (riscv_symbol_is_valid): New function.
2018-09-20Andes Technology has good news for you, we plan to update the nds32 port of ↵Nick Clifton1-0/+5
binutils on upstream! We have not only removed all unsupported and obsolete code, but also supported lost of new features, including better link-time relaxations and TLS implementations. Besides, the files generated by the newly assembler and linker usually get higher performance and more optimized code size. ld * emultempl/nds32elf.em (hyper_relax): New variable. (nds32_elf_create_output_section_statements): the parameters of bfd_elf32_nds32_set_target_option (PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS, PARSE_AND_LIST_ARGS_CASES): Add new option --mhyper-relax. * emultempl/nds32elf.em (nds32_elf_after_open): Updated. * emultempl/nds32elf.em (tls_desc_trampoline): New variable. * (nds32_elf_create_output_section_statements): Updated. * (nds32_elf_after_parse): Disable relaxations when PIC is enable. * (PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS, PARSE_AND_LIST_ARGS_CASES): Add new option --m[no-]tlsdesc-trampoline. include * elf/nds32.h: Remove the unused target features. * dis-asm.h (disassemble_init_nds32): Declared. * elf/nds32.h (E_NDS32_NULL): Removed. (E_NDS32_HAS_DSP_INST, E_NDS32_HAS_ZOL): New. * opcode/nds32.h: Ident. (N32_SUB6, INSN_LW): New macros. (enum n32_opcodes): Updated. * elf/nds32.h: Doc fixes. * elf/nds32.h: Add R_NDS32_LSI. * elf/nds32.h: Add new relocations for TLS. gas * config/tc-nds32.c: Remove the unused target features. (nds32_relax_relocs, md_pseudo_table, nds32_elf_record_fixup_exp, nds32_set_elf_flags_by_insn, nds32_insert_relax_entry, nds32_apply_fix): Likewise. (nds32_no_ex9_begin): Removed. * config/tc-nds32.c (add_mapping_symbol_for_align, make_mapping_symbol, add_mapping_symbol): New functions. * config/tc-nds32.h (enum mstate): New. (nds32_segment_info_type): Likewise. * configure.ac (--enable-dsp-ext, --enable-zol-ext): New options. * config.in: Regenerated. * configure: Regenerated. * config/tc-nds32.c (nds32_dx_regs): Set the value according to the configuration. (nds32_perf_ext, nds32_perf_ext2, nds32_string_ext, nds32_audio_ext): Likewise. (nds32_dsp_ext): New variable. Set the value according to the configuration. (nds32_zol_ext): Likewise. (asm_desc, nds32_pseudo_opcode_table): Make them static. (nds32_set_elf_flags_by_insn): Updated. (nds32_check_insn_available): Updated. (nds32_str_tolower): New function. * config/tc-nds32.c (relax_table): Updated. (md_begin): Updated. (md_assemble): Use XNEW macro to allocate space for `insn.info', and then remember to free it. (md_section_align): Cast (-1) to ValueT. (nds32_get_align): Cast (~0U) to addressT. (nds32_relax_branch_instructions): Updated. (md_convert_frag): Add new local variable `final_r_type'. (invalid_prev_frag): Add new bfd_boolean parameter `relax'. All callers changed. * config/tc-nds32.c (struct nds32_relocs_pattern): Add `insn' field. (struct nds32_hint_map): Add `option_list' field. (struct suffix_name, suffix_table): Remove the unused `pic' field. (do_pseudo_b, do_pseudo_bal): Remove the suffix checking. (do_pseudo_la_internal, do_pseudo_pushpopm): Indent. (relax_hint_bias, relax_hint_id_current): New static variables. (reset_bias, relax_hint_begin): New variables. (nds_itoa): New function. (CLEAN_REG, GET_OPCODE): New macros. (struct relax_hint_id): New. (nds32_relax_hint): For .relax_hint directive, we can use `begin' and `end' to mark the relax pattern without giving exactly id number. (nds32_elf_append_relax_relocs): Handle the case that the .relax_hint directives are attached to pseudo instruction. (nds32_elf_save_pseudo_pattern): Change the second parameter from instruction's opcode to byte code. (nds32_elf_build_relax_relation): Add new bfd_boolean parameter `pseudo_hint'. (nds32_lookup_pseudo_opcode): Fix the overflow issue. (enum nds32_insn_type): Add N32_RELAX_ALU1 and N32_RELAX_16BIT. (nds32_elf_record_fixup_exp, relax_ls_table, hint_map, nds32_find_reloc_table, nds32_match_hint_insn, nds32_parse_name): Updated. * config/tc-nds32.h (MAX_RELAX_NUM): Extend it to 6. (enum nds32_relax_hint_type): Merge NDS32_RELAX_HINT_LA and NDS32_RELAX_HINT_LS into NDS32_RELAX_HINT_LALS. Add NDS32_RELAX_HINT_LA_PLT, NDS32_RELAX_HINT_LA_GOT and NDS32_RELAX_HINT_LA_GOTOFF. * config/tc-nds32.h (relax_ls_table): Add floating load/store to gp relax pattern. (hint_map, nds32_find_reloc_table): Likewise. * configure.ac: Define NDS32_LINUX_TOOLCHAIN. * configure: Regenerated. * config.in: Regenerated. * config/tc-nds32.h (enum nds32_ramp): Updated. (enum nds32_relax_hint_type): Likewise. * config/tc-nds32.c: Include "errno.h" and "limits.h". (relax_ls_table): Add TLS relax patterns. (nds32_elf_append_relax_relocs): Attach BFD_RELOC_NDS32_GROUP on each instructions of TLS patterns. (nds32_elf_record_fixup_exp): Updated. (nds32_apply_fix): Likewise. (suffix_table): Add TLSDESC suffix. binutils* testsuite/binutils-all/objcopy.exp: Set the unsupported reloc number from 215 to 255 for NDS32. bfd * elf32-nds32.c (nds32_elf_relax_loadstore): Remove the unused target features. (bfd_elf32_nds32_set_target_option): Remove the unused parameters. (nds32_elf_relax_piclo12, nds32_elf_relax_letlslo12, nds32_elf_relax_letlsadd, nds32_elf_relax_letlsls, nds32_elf_relax_pltgot_suff, nds32_elf_relax_got_suff nds32_elf_relax_gotoff_suff, calculate_plt_memory_address, calculate_plt_offset, calculate_got_memory_address, nds32_elf_check_dup_relocs): Removed. All callers changed. * elf32-nds32.h: Remove the unused macros and defines. (elf_nds32_link_hash_table): Remove the unused variable. (bfd_elf32_nds32_set_target_option): Update prototype. (nds32_elf_ex9_init): Removed. * elf32-nds32.c (nds32_convert_32_to_16): Updated. * elf32-nds32.c (HOWTO2, HOWTO3): Define new HOWTO macros to initialize array nds32_elf_howto_table in any order without lots of EMPTY_HOWTO. (nds32_reloc_map): Updated. * reloc.c: Add BFD_RELOC_NDS32_LSI. * bfd-in2.h: Regenerated. * bfd/libbfd.h: Regenerated. * elf32-nds32.c (nds32_elf_relax_howto_table): Add R_NDS32_LSI. (nds32_reloc_map): Likewise. (nds32_elf_relax_flsi): New function. (nds32_elf_relax_section): Support floating load/store relaxation. * elf32-nds32.c (NDS32_GUARD_SEC_P, elf32_nds32_local_gp_offset): New macro. (struct elf_nds32_link_hash_entry): New `offset_to_gp' field. (struct elf_nds32_obj_tdata): New `offset_to_gp' and `hdr_size' fields. (elf32_nds32_allocate_local_sym_info, nds32_elf_relax_guard, nds32_elf_is_target_special_symbol, nds32_elf_maybe_function_sym): New functions. (nds32_info_to_howto_rel): Add BFD_ASSERT. (bfd_elf32_bfd_reloc_type_table_lookup, nds32_elf_link_hash_newfunc, nds32_elf_link_hash_table_create, nds32_elf_relocate_section, nds32_elf_relax_loadstore, nds32_elf_relax_lo12, nds32_relax_adjust_label, bfd_elf32_nds32_set_target_option, nds32_fag_mark_relax): Updated. (nds32_elf_final_sda_base): Improve it to find the better gp value. (insert_nds32_elf_blank): Must consider `len' when inserting blanks. * elf32-nds32.h (bfd_elf32_nds32_set_target_option): Update prototype. (struct elf_nds32_link_hash_table): Add new variable `hyper_relax'. * elf32-nds32.c (elf32_nds32_allocate_dynrelocs): New function. (create_got_section): Likewise. (allocate_dynrelocs, nds32_elf_size_dynamic_sections, nds32_elf_relocate_section, nds32_elf_finish_dynamic_symbol): Updated. (nds32_elf_check_relocs): Fix the issue that the shared library may has TEXTREL entry in the dynamic section. (nds32_elf_create_dynamic_sections): Enable to call readonly_dynrelocs since the TEXTREL issue is fixed in the nds32_elf_check_relocs. (nds32_elf_finish_dynamic_sections): Update and add DT_RELASZ dynamic entry. (calculate_offset): Remove the unused parameter `pic_ext_target' and related codes. All callers changed. (elf_backend_dtrel_excludes_plt): Disable it temporarily since it will cause some errors for our test cases. * elf32-nds32.c (nds32_elf_merge_private_bfd_data): Allow to link the generic object. * reloc.c: Add TLS relocations. * libbfd.h: Regenerated. * bfd-in2.h: Regenerated. * elf32-nds32.h (struct section_id_list_t): New. (elf32_nds32_lookup_section_id, elf32_nds32_check_relax_group, elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model): New prototypes. (elf32_nds32_compute_jump_table_size, elf32_nds32_local_tlsdesc_gotent): New macro. (nds32_insertion_sort, bfd_elf32_nds32_set_target_option, elf_nds32_link_hash_table): Updated. * elf32-nds32.c (enum elf_nds32_tls_type): New. (struct elf32_nds32_relax_group_t, struct relax_group_list_t): New. (elf32_nds32_add_dynreloc, patch_tls_desc_to_ie, get_tls_type, fls, ones32, list_insert, list_insert_sibling, dump_chain, elf32_nds32_check_relax_group, elf32_nds32_lookup_section_id, elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model): New functions. (elf_nds32_obj_tdata): Add new fields. (elf32_nds32_relax_group_ptr, nds32_elf_local_tlsdesc_gotent): New macros. (nds32_elf_howto_table): Add TLS relocations. (nds32_reloc_map): Likewise. (nds32_elf_copy_indirect_symbol, nds32_elf_size_dynamic_sections, nds32_elf_finish_dynamic_symbol, elf32_nds32_allocate_local_sym_info, nds32_elf_relocate_section, bfd_elf32_nds32_set_target_option, nds32_elf_check_relocs, allocate_dynrelocs): Updated. (nds32_elf_relax_section): Call nds32_elf_unify_tls_model. (dtpoff_base): Rename it to `gottpof' and then update it. opcodes * nds32-asm.c (operand_fields): Remove the unused fields. (nds32_opcodes): Remove the unused instructions. * nds32-dis.c (nds32_ex9_info): Removed. (nds32_parse_opcode): Updated. (print_insn_nds32): Likewise. * nds32-asm.c (config.h, stdlib.h, string.h): New includes. (LEX_SET_FIELD, LEX_GET_FIELD): Update defines. (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table, build_opcode_hash_table): New functions. (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table, nds32_opcode_table): New. (hw_ktabs): Declare it to a pointer rather than an array. (build_hash_table): Removed. * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT, SYN_ROPT and upadte HW_GPR and HW_INT. * nds32-dis.c (keywords): Remove const. (match_field): New function. (nds32_parse_opcode): Updated. * disassemble.c (disassemble_init_for_target): Add disassemble_init_nds32. * nds32-dis.c (eum map_type): New. (nds32_private_data): Likewise. (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid, nds32_add_opcode_hash_table, disassemble_init_nds32): New functions. (print_insn_nds32): Updated. * nds32-asm.c (parse_aext_reg): Add new parameter. (parse_re, parse_re2, parse_aext_reg): Only reduced registers are allowed to use. All callers changed. * nds32-asm.c (keyword_usr, keyword_sr): Updated. (operand_fields): Add new fields. (nds32_opcodes): Add new instructions. (keyword_aridxi_mx): New keyword. * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX and NASM_ATTR_ZOL. (ALU2_1, ALU2_2, ALU2_3): New macros. * nds32-dis.c (nds32_filter_unknown_insn): Updated.
2018-09-08S12Z: Make disassebler work for --enable-targets=all config.John Darrington1-0/+1
opcodes/ * disassemble.c (ARCH_s12z): Define if ARCH_all.
2018-07-30Add support for the C_SKY series of processors.Andrew Jenner1-0/+14
This patch series is a new binutils port for C-SKY processors, including support for both the V1 and V2 processor variants. V1 is derived from the MCore architecture while V2 is substantially different, with mixed 16- and 32-bit instructions, a larger register set, a different (but overlapping) ABI, etc. There is support for bare-metal ELF targets and Linux with both glibc and uClibc. This code is being contributed jointly by C-SKY Microsystems and Mentor Graphics. C-SKY is responsible for the technical content and has proposed Lifang Xia and Yunhai Shang as port maintainers. (Note that C-SKY does have a corporate copyright assignment on file with the FSF.) Mentor Graphics' role has been cleaning up the code, adding documentation and additional test cases, etc, to address issues we anticipated reviewers would complain about. bfd * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES): Add C-SKY. (BFD32_BACKENDS, BFD_BACKENDS_CFILES): Likewise. * Makefile.in: Regenerated. * archures.c (enum bfd_architecture): Add bfd_arch_csky and related bfd_mach defines. (bfd_csky_arch): Declare. (bfd_archures_list): Add C-SKY. * bfd-in.h (elf32_csky_build_stubs): Declare. (elf32_csky_size_stubs): Declare. (elf32_csky_next_input_section: Declare. (elf32_csky_setup_section_lists): Declare. * bfd-in2.h: Regenerated. * config.bfd: Add C-SKY. * configure.ac: Likewise. * configure: Regenerated. * cpu-csky.c: New file. * elf-bfd.h (enum elf_target_id): Add C-SKY. * elf32-csky.c: New file. * libbfd.h: Regenerated. * reloc.c: Add C-SKY relocations. * targets.c (csky_elf32_be_vec, csky_elf32_le_vec): Declare. (_bfd_target_vector): Add C-SKY target vector entries. binutils* readelf.c: Include elf/csky.h. (guess_is_rela): Handle EM_CSKY. (dump_relocations): Likewise. (get_machine_name): Likewise. (is_32bit_abs_reloc): Likewise. include * dis-asm.h (csky_symbol_is_valid): Declare. * opcode/csky.h: New file. opcodes * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c. * Makefile.in: Regenerated. * configure.ac: Add C-SKY. * configure: Regenerated. * csky-dis.c: New file. * csky-opc.h: New file. * disassemble.c (ARCH_csky): Define. (disassembler, disassemble_init_for_target): Add case for ARCH_csky. * disassemble.h (print_insn_csky, csky_get_disassembler): Declare. gas * Makefile.am (TARGET_CPU_CFILES): Add entry for C-SKY. (TARGET_CPU_HFILES, TARGET_ENV_HFILES): Likewise. * Makefile.in: Regenerated. * config/tc-csky.c: New file. * config/tc-csky.h: New file. * config/te-csky_abiv1.h: New file. * config/te-csky_abiv1_linux.h: New file. * config/te-csky_abiv2.h: New file. * config/te-csky_abiv2_linux.h: New file. * configure.tgt: Add C-SKY. * doc/Makefile.am (CPU_DOCS): Add entry for C-SKY. * doc/Makefile.in: Regenerated. * doc/all.texi: Set CSKY feature. * doc/as.texi (Overview): Add C-SKY options. (Machine Dependencies): Likewise. * doc/c-csky.texi: New file. * testsuite/gas/csky/*: New test cases. ld * Makefile.am (ALL_EMULATION_SOURCES): Add C-SKY emulations. (ecskyelf.c, ecskyelf_linux.c): New rules. * Makefile.in: Regenerated. * configure.tgt: Add C-SKY. * emulparams/cskyelf.sh: New file. * emulparams/cskyelf_linux.sh: New file. * emultempl/cskyelf.em: New file. * gen-doc.texi: Add C-SKY. * ld.texi: Likewise. (Options specific to C-SKY targets): New section. * testsuite/ld-csky/*: New tests.
2018-05-18Add support for the Freescale s12z processor.John Darrington1-0/+5
bfd * Makefile.am: Add s12z files. * Makefile.in: Regenerate. * archures.c: Add bfd_s12z_arch. * bfd-in.h: Add exports of bfd_putb24 and bfd_putl24. * bfd-in2.h: Regenerate. * config.bfd: Add s12z target. * configure.ac: Add s12z target. * configure: Regenerate. * cpu-s12z.c: New file. * elf32-s12z.c: New file. * libbfd.c (bfd_putb24): New function. (bfd_putl24): New function. * libbfd.h: Regenerate. * reloc.c: Add s12z relocations. (bfd_get_reloc_size): Handle size 5 relocs. * targets.c: Add s12z_elf32_vec. opcodes * Makefile.am: Add support for s12z architecture. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * s12z-dis.c: New file. * s12z.h: New file. include * elf/s12z.h: New header. ld * Makefile.am: Add support for s12z architecture. * configure.tgt: Likewise. * Makefile.in: Regenerate. * emulparams/m9s12zelf.sh: New file. * scripttempl/elfm9s12z.sc: New file. * testsuite/ld-discard/static.d: Expect to fail for the s12z target. * testsuite/ld-elf/endsym.d: Likewise. * testsuite/ld-elf/merge.d: Likewise. * testsuite/ld-elf/pr14926.d: Skip for the s12z target. * testsuite/ld-elf/sec64k.exp: Likewise. * testsuite/ld-s12z: New directory. * testsuite/ld-s12z/opr-linking.d: New file. * testsuite/ld-s12z/opr-linking.s: New file. * testsuite/ld-s12z/relative-linking.d: New file. * testsuite/ld-s12z/relative-linking.s: New file. * testsuite/ld-s12z/z12s.exp: New file. gas * Makefile.am: Add support for s12z target. * Makefile.in: Regenerate. * NEWS: Mention the new support. * config/tc-s12z.c: New file. * config/tc-s12z.h: New file. * configure.tgt: Add s12z support. * doc/Makefile.am: Likewise. * doc/Makefile.in: Regenerate. * doc/all.texi: Add s12z documentation. * doc/as.textinfo: Likewise. * doc/c-s12z.texi: New file. * testsuite/gas/s12z: New directory. * testsuite/gas/s12z/abs.d: New file. * testsuite/gas/s12z/abs.s: New file. * testsuite/gas/s12z/adc-imm.d: New file. * testsuite/gas/s12z/adc-imm.s: New file. * testsuite/gas/s12z/adc-opr.d: New file. * testsuite/gas/s12z/adc-opr.s: New file. * testsuite/gas/s12z/add-imm.d: New file. * testsuite/gas/s12z/add-imm.s: New file. * testsuite/gas/s12z/add-opr.d: New file. * testsuite/gas/s12z/add-opr.s: New file. * testsuite/gas/s12z/and-imm.d: New file. * testsuite/gas/s12z/and-imm.s: New file. * testsuite/gas/s12z/and-opr.d: New file. * testsuite/gas/s12z/and-opr.s: New file. * testsuite/gas/s12z/and-or-cc.d: New file. * testsuite/gas/s12z/and-or-cc.s: New file. * testsuite/gas/s12z/bfext-special.d: New file. * testsuite/gas/s12z/bfext-special.s: New file. * testsuite/gas/s12z/bfext.d: New file. * testsuite/gas/s12z/bfext.s: New file. * testsuite/gas/s12z/bit-manip.d: New file. * testsuite/gas/s12z/bit-manip.s: New file. * testsuite/gas/s12z/bit.d: New file. * testsuite/gas/s12z/bit.s: New file. * testsuite/gas/s12z/bra-expression-defined.d: New file. * testsuite/gas/s12z/bra-expression-defined.s: New file. * testsuite/gas/s12z/bra-expression-undef.d: New file. * testsuite/gas/s12z/bra-expression-undef.s: New file. * testsuite/gas/s12z/bra.d: New file. * testsuite/gas/s12z/bra.s: New file. * testsuite/gas/s12z/brclr-symbols.d: New file. * testsuite/gas/s12z/brclr-symbols.s: New file. * testsuite/gas/s12z/brset-clr-opr-imm-rel.d: New file. * testsuite/gas/s12z/brset-clr-opr-imm-rel.s: New file. * testsuite/gas/s12z/brset-clr-opr-reg-rel.d: New file. * testsuite/gas/s12z/brset-clr-opr-reg-rel.s: New file. * testsuite/gas/s12z/brset-clr-reg-imm-rel.d: New file. * testsuite/gas/s12z/brset-clr-reg-imm-rel.s: New file. * testsuite/gas/s12z/brset-clr-reg-reg-rel.d: New file. * testsuite/gas/s12z/brset-clr-reg-reg-rel.s: New file. * testsuite/gas/s12z/clb.d: New file. * testsuite/gas/s12z/clb.s: New file. * testsuite/gas/s12z/clr-opr.d: New file. * testsuite/gas/s12z/clr-opr.s: New file. * testsuite/gas/s12z/clr.d: New file. * testsuite/gas/s12z/clr.s: New file. * testsuite/gas/s12z/cmp-imm.d: New file. * testsuite/gas/s12z/cmp-imm.s: New file. * testsuite/gas/s12z/cmp-opr-inc.d: New file. * testsuite/gas/s12z/cmp-opr-inc.s: New file. * testsuite/gas/s12z/cmp-opr-rdirect.d: New file. * testsuite/gas/s12z/cmp-opr-rdirect.s: New file. * testsuite/gas/s12z/cmp-opr-reg.d: New file. * testsuite/gas/s12z/cmp-opr-reg.s: New file. * testsuite/gas/s12z/cmp-opr-rindirect.d: New file. * testsuite/gas/s12z/cmp-opr-rindirect.s: New file. * testsuite/gas/s12z/cmp-opr-sxe4.d: New file. * testsuite/gas/s12z/cmp-opr-sxe4.s: New file. * testsuite/gas/s12z/cmp-opr-xys.d: New file. * testsuite/gas/s12z/cmp-opr-xys.s: New file. * testsuite/gas/s12z/cmp-s-imm.d: New file. * testsuite/gas/s12z/cmp-s-imm.s: New file. * testsuite/gas/s12z/cmp-s-opr.d: New file. * testsuite/gas/s12z/cmp-s-opr.s: New file. * testsuite/gas/s12z/cmp-xy.d: New file. * testsuite/gas/s12z/cmp-xy.s: New file. * testsuite/gas/s12z/com-opr.d: New file. * testsuite/gas/s12z/com-opr.s: New file. * testsuite/gas/s12z/complex-shifts.d: New file. * testsuite/gas/s12z/complex-shifts.s: New file. * testsuite/gas/s12z/db-tb-cc-opr.d: New file. * testsuite/gas/s12z/db-tb-cc-opr.s: New file. * testsuite/gas/s12z/db-tb-cc-reg.d: New file. * testsuite/gas/s12z/db-tb-cc-reg.s: New file. * testsuite/gas/s12z/dbCC.d: New file. * testsuite/gas/s12z/dbCC.s: New file. * testsuite/gas/s12z/dec-opr.d: New file. * testsuite/gas/s12z/dec-opr.s: New file. * testsuite/gas/s12z/dec.d: New file. * testsuite/gas/s12z/dec.s: New file. * testsuite/gas/s12z/div.d: New file. * testsuite/gas/s12z/div.s: New file. * testsuite/gas/s12z/eor.d: New file. * testsuite/gas/s12z/eor.s: New file. * testsuite/gas/s12z/exg.d: New file. * testsuite/gas/s12z/exg.s: New file. * testsuite/gas/s12z/ext24-ld-xy.d: New file. * testsuite/gas/s12z/ext24-ld-xy.s: New file. * testsuite/gas/s12z/inc-opr.d: New file. * testsuite/gas/s12z/inc-opr.s: New file. * testsuite/gas/s12z/inc.d: New file. * testsuite/gas/s12z/inc.s: New file. * testsuite/gas/s12z/inh.d: New file. * testsuite/gas/s12z/inh.s: New file. * testsuite/gas/s12z/jmp.d: New file. * testsuite/gas/s12z/jmp.s: New file. * testsuite/gas/s12z/jsr.d: New file. * testsuite/gas/s12z/jsr.s: New file. * testsuite/gas/s12z/ld-imm-page2.d: New file. * testsuite/gas/s12z/ld-imm-page2.s: New file. * testsuite/gas/s12z/ld-imm.d: New file. * testsuite/gas/s12z/ld-imm.s: New file. * testsuite/gas/s12z/ld-immu18.d: New file. * testsuite/gas/s12z/ld-immu18.s: New file. * testsuite/gas/s12z/ld-large-direct.d: New file. * testsuite/gas/s12z/ld-large-direct.s: New file. * testsuite/gas/s12z/ld-opr.d: New file. * testsuite/gas/s12z/ld-opr.s: New file. * testsuite/gas/s12z/ld-s-opr.d: New file. * testsuite/gas/s12z/ld-s-opr.s: New file. * testsuite/gas/s12z/ld-small-direct.d: New file. * testsuite/gas/s12z/ld-small-direct.s: New file. * testsuite/gas/s12z/lea-immu18.d: New file. * testsuite/gas/s12z/lea-immu18.s: New file. * testsuite/gas/s12z/lea.d: New file. * testsuite/gas/s12z/lea.s: New file. * testsuite/gas/s12z/mac.d: New file. * testsuite/gas/s12z/mac.s: New file. * testsuite/gas/s12z/min-max.d: New file. * testsuite/gas/s12z/min-max.s: New file. * testsuite/gas/s12z/mod.d: New file. * testsuite/gas/s12z/mod.s: New file. * testsuite/gas/s12z/mov.d: New file. * testsuite/gas/s12z/mov.s: New file. * testsuite/gas/s12z/mul-imm.d: New file. * testsuite/gas/s12z/mul-imm.s: New file. * testsuite/gas/s12z/mul-opr-opr.d: New file. * testsuite/gas/s12z/mul-opr-opr.s: New file. * testsuite/gas/s12z/mul-opr.d: New file. * testsuite/gas/s12z/mul-opr.s: New file. * testsuite/gas/s12z/mul-reg.d: New file. * testsuite/gas/s12z/mul-reg.s: New file. * testsuite/gas/s12z/mul.d: New file. * testsuite/gas/s12z/mul.s: New file. * testsuite/gas/s12z/neg-opr.d: New file. * testsuite/gas/s12z/neg-opr.s: New file. * testsuite/gas/s12z/not-so-simple-shifts.d: New file. * testsuite/gas/s12z/not-so-simple-shifts.s: New file. * testsuite/gas/s12z/opr-18u.d: New file. * testsuite/gas/s12z/opr-18u.s: New file. * testsuite/gas/s12z/opr-expr.d: New file. * testsuite/gas/s12z/opr-expr.s: New file. * testsuite/gas/s12z/opr-ext-18.d: New file. * testsuite/gas/s12z/opr-ext-18.s: New file. * testsuite/gas/s12z/opr-idx-24-reg.d: New file. * testsuite/gas/s12z/opr-idx-24-reg.s: New file. * testsuite/gas/s12z/opr-idx3-reg.d: New file. * testsuite/gas/s12z/opr-idx3-reg.s: New file. * testsuite/gas/s12z/opr-idx3-xysp-24.d: New file. * testsuite/gas/s12z/opr-idx3-xysp-24.s: New file. * testsuite/gas/s12z/opr-indirect-expr.d: New file. * testsuite/gas/s12z/opr-indirect-expr.s: New file. * testsuite/gas/s12z/opr-symbol.d: New file. * testsuite/gas/s12z/opr-symbol.s: New file. * testsuite/gas/s12z/or-imm.d: New file. * testsuite/gas/s12z/or-imm.s: New file. * testsuite/gas/s12z/or-opr.d: New file. * testsuite/gas/s12z/or-opr.s: New file. * testsuite/gas/s12z/p2-mul.d: New file. * testsuite/gas/s12z/p2-mul.s: New file. * testsuite/gas/s12z/page2-inh.d: New file. * testsuite/gas/s12z/page2-inh.s: New file. * testsuite/gas/s12z/psh-pul.d: New file. * testsuite/gas/s12z/psh-pul.s: New file. * testsuite/gas/s12z/qmul.d: New file. * testsuite/gas/s12z/qmul.s: New file. * testsuite/gas/s12z/rotate.d: New file. * testsuite/gas/s12z/rotate.s: New file. * testsuite/gas/s12z/s12z.exp: New file. * testsuite/gas/s12z/sat.d: New file. * testsuite/gas/s12z/sat.s: New file. * testsuite/gas/s12z/sbc-imm.d: New file. * testsuite/gas/s12z/sbc-imm.s: New file. * testsuite/gas/s12z/sbc-opr.d: New file. * testsuite/gas/s12z/sbc-opr.s: New file. * testsuite/gas/s12z/shift.d: New file. * testsuite/gas/s12z/shift.s: New file. * testsuite/gas/s12z/simple-shift.d: New file. * testsuite/gas/s12z/simple-shift.s: New file. * testsuite/gas/s12z/single-ops.d: New file. * testsuite/gas/s12z/single-ops.s: New file. * testsuite/gas/s12z/specd6.d: New file. * testsuite/gas/s12z/specd6.s: New file. * testsuite/gas/s12z/st-large-direct.d: New file. * testsuite/gas/s12z/st-large-direct.s: New file. * testsuite/gas/s12z/st-opr.d: New file. * testsuite/gas/s12z/st-opr.s: New file. * testsuite/gas/s12z/st-s-opr.d: New file. * testsuite/gas/s12z/st-s-opr.s: New file. * testsuite/gas/s12z/st-small-direct.d: New file. * testsuite/gas/s12z/st-small-direct.s: New file. * testsuite/gas/s12z/st-xy.d: New file. * testsuite/gas/s12z/st-xy.s: New file. * testsuite/gas/s12z/sub-imm.d: New file. * testsuite/gas/s12z/sub-imm.s: New file. * testsuite/gas/s12z/sub-opr.d: New file. * testsuite/gas/s12z/sub-opr.s: New file. * testsuite/gas/s12z/tfr.d: New file. * testsuite/gas/s12z/tfr.s: New file. * testsuite/gas/s12z/trap.d: New file. * testsuite/gas/s12z/trap.s: New file. binutils* readelf.c: Add support for s12z architecture. * testsuite/lib/binutils-common.exp (is_elf_format): Excluse s12z targets.
2018-04-30This patch adds support to objdump for disassembly of NFP (Netronome Flow ↵Francois H. Theron1-0/+9
Processor) ELF files (.nffw) as well as some basic readelf support. bfd * Makefile.am: Added NFP files to build. * archures.c: Added bfd_arch_nfp * config.bfd: Added NFP support. * configure.ac: Added NFP support. * cpu-nfp.c: New, for NFP support. * elf-bfd.h: Added elf_section_info() * elf64-nfp.c: New, for NFP support. * po/SRC-POTFILES.in: Added NFP source files. * targets.c: Added nfp_elf64_vec * bfd-in2.h: Regenerate. * Makefile.in: Regenerate. * configure: Regenerate. binutils* readelf.c: Very basic support for EM_NFP and its section types. * testsuite/binutils-all/nfp: New directory. * testsuite/binutils-all/nfp/objdump.exp: New file. Run new tests. * testsuite/binutils-all/nfp/test2_ctx8.d: New file. * testsuite/binutils-all/nfp/test2_no-pc_ctx4.d: New file. * testsuite/binutils-all/nfp/test1.d: New file. * testsuite/binutils-all/nfp/nfp6000.nffw: New file. * testsuite/binutils-all/nfp/test2_nfp6000.nffw: New file. * NEWS: Mention the new support. include * dis-asm.h: Added print_nfp_disassembler_options prototype. * elf/common.h: Added EM_NFP, officially assigned. See Google Group Generic System V Application Binary Interface. * elf/nfp.h: New, for NFP support. * opcode/nfp.h: New, for NFP support. opcodes Makefile.am: Added nfp-dis.c. configure.ac: Added bfd_nfp_arch. disassemble.h: Added print_insn_nfp prototype. disassemble.c: Added ARCH_nfp and call to print_insn_nfp nfp-dis.c: New, for NFP support. po/POTFILES.in: Added nfp-dis.c to the list. Makefile.in: Regenerate. configure: Regenerate.
2018-04-16Remove sh5 and sh64 supportAlan Modra1-1/+0
include/ * dis-asm.h: Remove sh5 and sh64 support. bfd/ * Makefile.am: Remove sh5 and sh64 support. * archures.c: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * cpu-sh.c: Likewise. * elf32-sh-relocs.h: Likewise. * elf32-sh.c: Likewise. * targets.c: Likewise. * elf32-sh64-com.c: Delete. * elf32-sh64.c: Delete. * elf32-sh64.h: Delete. * elf64-sh64.c: Delete. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. opcodes/ * Makefile.am: Remove sh5 and sh64 support. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Likewise. * sh-dis.c: Likewise. * sh64-dis.c: Delete. * sh64-opc.c: Delete. * sh64-opc.h: Delete. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. bintuils/ * testsuite/binutils-all/objcopy.exp: Remove sh5 and sh64 support. gas/ * Makefile.am: Remove sh5 and sh64 support. * config/tc-sh.c: Likewise. * configure.tgt: Likewise. * doc/Makefile.am: Likewise. * doc/as.texinfo: Likewise. * testsuite/gas/cfi/cfi.exp: Likewise. * testsuite/gas/sh/basic.exp: Likewise. * config/tc-sh64.c: Delete. * config/tc-sh64.h: Delete. * doc/c-sh64.texi: Delete. * testsuite/gas/sh/sh64/abi-32.d: Delete. * testsuite/gas/sh/sh64/abi-32.s: Delete. * testsuite/gas/sh/sh64/abi-64.d: Delete. * testsuite/gas/sh/sh64/abi-64.s: Delete. * testsuite/gas/sh/sh64/basic-1.d: Delete. * testsuite/gas/sh/sh64/basic-1.s: Delete. * testsuite/gas/sh/sh64/case-1.d: Delete. * testsuite/gas/sh/sh64/case-1.s: Delete. * testsuite/gas/sh/sh64/case-noexp-1.d: Delete. * testsuite/gas/sh/sh64/crange1-1.d: Delete. * testsuite/gas/sh/sh64/crange1-2.d: Delete. * testsuite/gas/sh/sh64/crange1.s: Delete. * testsuite/gas/sh/sh64/crange2-1.d: Delete. * testsuite/gas/sh/sh64/crange2-2.d: Delete. * testsuite/gas/sh/sh64/crange2-noexp-1.d: Delete. * testsuite/gas/sh/sh64/crange2.s: Delete. * testsuite/gas/sh/sh64/crange3-1.d: Delete. * testsuite/gas/sh/sh64/crange3.s: Delete. * testsuite/gas/sh/sh64/crange4-1.d: Delete. * testsuite/gas/sh/sh64/crange4.s: Delete. * testsuite/gas/sh/sh64/crange5-1.d: Delete. * testsuite/gas/sh/sh64/crange5.s: Delete. * testsuite/gas/sh/sh64/creg-1.d: Delete. * testsuite/gas/sh/sh64/creg-1.s: Delete. * testsuite/gas/sh/sh64/creg-2.d: Delete. * testsuite/gas/sh/sh64/creg-2.s: Delete. * testsuite/gas/sh/sh64/datal-1.s: Delete. * testsuite/gas/sh/sh64/datal-2.d: Delete. * testsuite/gas/sh/sh64/datal-2.s: Delete. * testsuite/gas/sh/sh64/datal-3.s: Delete. * testsuite/gas/sh/sh64/datal32-1.d: Delete. * testsuite/gas/sh/sh64/datal32-3.d: Delete. * testsuite/gas/sh/sh64/datal64-1.d: Delete. * testsuite/gas/sh/sh64/datal64-3.d: Delete. * testsuite/gas/sh/sh64/eh-1.d: Delete. * testsuite/gas/sh/sh64/eh-1.s: Delete. * testsuite/gas/sh/sh64/endian-1.d: Delete. * testsuite/gas/sh/sh64/endian-1.s: Delete. * testsuite/gas/sh/sh64/endian-2.d: Delete. * testsuite/gas/sh/sh64/endian-2.s: Delete. * testsuite/gas/sh/sh64/err-1.s: Delete. * testsuite/gas/sh/sh64/err-2.s: Delete. * testsuite/gas/sh/sh64/err-3.s: Delete. * testsuite/gas/sh/sh64/err-4.s: Delete. * testsuite/gas/sh/sh64/err-abi-32.s: Delete. * testsuite/gas/sh/sh64/err-abi-64.s: Delete. * testsuite/gas/sh/sh64/err-dsp.s: Delete. * testsuite/gas/sh/sh64/err-movi-noexp-1.s: Delete. * testsuite/gas/sh/sh64/err-noexp-cmd1.s: Delete. * testsuite/gas/sh/sh64/err-pt-1.s: Delete. * testsuite/gas/sh/sh64/err-pt32-cmd1.s: Delete. * testsuite/gas/sh/sh64/err-pt32-cmd2.s: Delete. * testsuite/gas/sh/sh64/err-pt32-cmd3.s: Delete. * testsuite/gas/sh/sh64/err-ptb-1.s: Delete. * testsuite/gas/sh/sh64/err-ptb-2.s: Delete. * testsuite/gas/sh/sh64/err.exp: Delete. * testsuite/gas/sh/sh64/immexpr1.s: Delete. * testsuite/gas/sh/sh64/immexpr2.s: Delete. * testsuite/gas/sh/sh64/immexpr32-1.d: Delete. * testsuite/gas/sh/sh64/immexpr32-2.d: Delete. * testsuite/gas/sh/sh64/immexpr64-1.d: Delete. * testsuite/gas/sh/sh64/immexpr64-2.d: Delete. * testsuite/gas/sh/sh64/lineno.d: Delete. * testsuite/gas/sh/sh64/lineno.s: Delete. * testsuite/gas/sh/sh64/localcom-1.d: Delete. * testsuite/gas/sh/sh64/localcom-1.s: Delete. * testsuite/gas/sh/sh64/mix-1.d: Delete. * testsuite/gas/sh/sh64/mix-1.s: Delete. * testsuite/gas/sh/sh64/mix-noexp-1.d: Delete. * testsuite/gas/sh/sh64/movi-1.s: Delete. * testsuite/gas/sh/sh64/movi-2.s: Delete. * testsuite/gas/sh/sh64/movi-3.d: Delete. * testsuite/gas/sh/sh64/movi-3.s: Delete. * testsuite/gas/sh/sh64/movi32-1.d: Delete. * testsuite/gas/sh/sh64/movi32-2.d: Delete. * testsuite/gas/sh/sh64/movi32-noexp-2.d: Delete. * testsuite/gas/sh/sh64/movi64-1.d: Delete. * testsuite/gas/sh/sh64/movi64-2.d: Delete. * testsuite/gas/sh/sh64/movi64-2.s: Delete. * testsuite/gas/sh/sh64/movi64-3.d: Delete. * testsuite/gas/sh/sh64/movi64-noexp-2.d: Delete. * testsuite/gas/sh/sh64/pt-1.d: Delete. * testsuite/gas/sh/sh64/pt-1.s: Delete. * testsuite/gas/sh/sh64/pt-2.s: Delete. * testsuite/gas/sh/sh64/pt-noexp-1.d: Delete. * testsuite/gas/sh/sh64/pt32-1.d: Delete. * testsuite/gas/sh/sh64/pt32-noexp-2.d: Delete. * testsuite/gas/sh/sh64/pt64-1.d: Delete. * testsuite/gas/sh/sh64/pt64-32-1.d: Delete. * testsuite/gas/sh/sh64/pt64-32-2.d: Delete. * testsuite/gas/sh/sh64/pt64-noexp-2.d: Delete. * testsuite/gas/sh/sh64/ptc-1.s: Delete. * testsuite/gas/sh/sh64/ptc32-1.d: Delete. * testsuite/gas/sh/sh64/ptc32-noexp-1.d: Delete. * testsuite/gas/sh/sh64/ptc64-1.d: Delete. * testsuite/gas/sh/sh64/ptc64-32-1.d: Delete. * testsuite/gas/sh/sh64/ptc64-noexp-1.d: Delete. * testsuite/gas/sh/sh64/ptext-1.s: Delete. * testsuite/gas/sh/sh64/ptext32-1.d: Delete. * testsuite/gas/sh/sh64/ptext32-noexp-1.d: Delete. * testsuite/gas/sh/sh64/ptext64-1.d: Delete. * testsuite/gas/sh/sh64/ptext64-32-1.d: Delete. * testsuite/gas/sh/sh64/ptext64-noexp-1.d: Delete. * testsuite/gas/sh/sh64/rel-1.s: Delete. * testsuite/gas/sh/sh64/rel-2.s: Delete. * testsuite/gas/sh/sh64/rel-3.s: Delete. * testsuite/gas/sh/sh64/rel-4.s: Delete. * testsuite/gas/sh/sh64/rel-5.s: Delete. * testsuite/gas/sh/sh64/rel32-1.d: Delete. * testsuite/gas/sh/sh64/rel32-2.d: Delete. * testsuite/gas/sh/sh64/rel32-3.d: Delete. * testsuite/gas/sh/sh64/rel32-4.d: Delete. * testsuite/gas/sh/sh64/rel32-5.d: Delete. * testsuite/gas/sh/sh64/rel64-1.d: Delete. * testsuite/gas/sh/sh64/rel64-2.d: Delete. * testsuite/gas/sh/sh64/rel64-3.d: Delete. * testsuite/gas/sh/sh64/rel64-4.d: Delete. * testsuite/gas/sh/sh64/rel64-5.d: Delete. * testsuite/gas/sh/sh64/relax-1.d: Delete. * testsuite/gas/sh/sh64/relax-1.s: Delete. * testsuite/gas/sh/sh64/relax-2.d: Delete. * testsuite/gas/sh/sh64/relax-2.s: Delete. * testsuite/gas/sh/sh64/relax-3.d: Delete. * testsuite/gas/sh/sh64/relax-3.s: Delete. * testsuite/gas/sh/sh64/sh64.exp: Delete. * testsuite/gas/sh/sh64/shift-1.s: Delete. * testsuite/gas/sh/sh64/shift-2.s: Delete. * testsuite/gas/sh/sh64/shift-3.s: Delete. * testsuite/gas/sh/sh64/shift32-1.d: Delete. * testsuite/gas/sh/sh64/shift32-3.d: Delete. * testsuite/gas/sh/sh64/shift32-noexp-3.d: Delete. * testsuite/gas/sh/sh64/shift64-1.d: Delete. * testsuite/gas/sh/sh64/shift64-2.d: Delete. * testsuite/gas/sh/sh64/shift64-3.d: Delete. * testsuite/gas/sh/sh64/shift64-noexp-3.d: Delete. * testsuite/gas/sh/sh64/syntax-1.d: Delete. * testsuite/gas/sh/sh64/syntax-1.s: Delete. * testsuite/gas/sh/sh64/syntax-2.d: Delete. * testsuite/gas/sh/sh64/syntax-2.s: Delete. * testsuite/gas/sh/sh64/ua-1.s: Delete. * testsuite/gas/sh/sh64/ua32-1.d: Delete. * testsuite/gas/sh/sh64/ua64-1.d: Delete. * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. * po/POTFILES.in: Regenerate. ld/ * Makefile.am: Remove sh5 and sh64 support. * configure.tgt: Likewise. * ldlang.c: Likewise. * testsuite/ld-elfcomm/elfcomm.exp: Likewise. * testsuite/ld-gc/gc.exp: Likewise. * testsuite/ld-gc/pr13683.d: Likewise. * testsuite/ld-scripts/crossref.exp: Likewise. * testsuite/ld-selective/selective.exp: Likewise. * testsuite/ld-sh/ld-r-1.d: Likewise. * testsuite/ld-sh/rd-sh.exp: Likewise. * testsuite/ld-sh/sh.exp: Likewise. * testsuite/ld-srec/srec.exp: Likewise. * testsuite/ld-undefined/undefined.exp: Likewise. * emulparams/shelf32.sh: Delete. * emulparams/shelf32_linux.sh: Delete. * emulparams/shelf32_nbsd.sh: Delete. * emulparams/shelf64.sh: Delete. * emulparams/shelf64_nbsd.sh: Delete. * emulparams/shlelf32.sh: Delete. * emulparams/shlelf32_linux.sh: Delete. * emulparams/shlelf32_nbsd.sh: Delete. * emulparams/shlelf64.sh: Delete. * emulparams/shlelf64_nbsd.sh: Delete. * emultempl/sh64elf.em: Delete. * testsuite/ld-sh/sh64/abi32.sd: Delete. * testsuite/ld-sh/sh64/abi32.xd: Delete. * testsuite/ld-sh/sh64/abi64.sd: Delete. * testsuite/ld-sh/sh64/abi64.xd: Delete. * testsuite/ld-sh/sh64/abixx-noexp.sd: Delete. * testsuite/ld-sh/sh64/cmpct1.sd: Delete. * testsuite/ld-sh/sh64/cmpct1.xd: Delete. * testsuite/ld-sh/sh64/crange-1.s: Delete. * testsuite/ld-sh/sh64/crange-2a.s: Delete. * testsuite/ld-sh/sh64/crange-2b.s: Delete. * testsuite/ld-sh/sh64/crange-2c.s: Delete. * testsuite/ld-sh/sh64/crange-2d.s: Delete. * testsuite/ld-sh/sh64/crange-2e.s: Delete. * testsuite/ld-sh/sh64/crange-2f.s: Delete. * testsuite/ld-sh/sh64/crange-2g.s: Delete. * testsuite/ld-sh/sh64/crange-2h.s: Delete. * testsuite/ld-sh/sh64/crange-2i.s: Delete. * testsuite/ld-sh/sh64/crange1.rd: Delete. * testsuite/ld-sh/sh64/crange2.rd: Delete. * testsuite/ld-sh/sh64/crange3-cmpct.rd: Delete. * testsuite/ld-sh/sh64/crange3-media.rd: Delete. * testsuite/ld-sh/sh64/crange3.dd: Delete. * testsuite/ld-sh/sh64/crange3.rd: Delete. * testsuite/ld-sh/sh64/crangerel1.rd: Delete. * testsuite/ld-sh/sh64/crangerel2.rd: Delete. * testsuite/ld-sh/sh64/dlsection-1.s: Delete. * testsuite/ld-sh/sh64/dlsection.sd: Delete. * testsuite/ld-sh/sh64/endian.dbd: Delete. * testsuite/ld-sh/sh64/endian.dld: Delete. * testsuite/ld-sh/sh64/endian.ld: Delete. * testsuite/ld-sh/sh64/endian.s: Delete. * testsuite/ld-sh/sh64/endian.sbd: Delete. * testsuite/ld-sh/sh64/endian.sld: Delete. * testsuite/ld-sh/sh64/gotplt.d: Delete. * testsuite/ld-sh/sh64/gotplt.map: Delete. * testsuite/ld-sh/sh64/gotplt.s: Delete. * testsuite/ld-sh/sh64/init-cmpct.d: Delete. * testsuite/ld-sh/sh64/init-media.d: Delete. * testsuite/ld-sh/sh64/init.s: Delete. * testsuite/ld-sh/sh64/init64.d: Delete. * testsuite/ld-sh/sh64/mix1-noexp.sd: Delete. * testsuite/ld-sh/sh64/mix1.sd: Delete. * testsuite/ld-sh/sh64/mix1.xd: Delete. * testsuite/ld-sh/sh64/mix2-noexp.sd: Delete. * testsuite/ld-sh/sh64/mix2.sd: Delete. * testsuite/ld-sh/sh64/mix2.xd: Delete. * testsuite/ld-sh/sh64/rd-sh64.exp: Delete. * testsuite/ld-sh/sh64/rel-1.s: Delete. * testsuite/ld-sh/sh64/rel-2.s: Delete. * testsuite/ld-sh/sh64/rel32.xd: Delete. * testsuite/ld-sh/sh64/rel64.xd: Delete. * testsuite/ld-sh/sh64/relax.exp: Delete. * testsuite/ld-sh/sh64/relax1.s: Delete. * testsuite/ld-sh/sh64/relax2.s: Delete. * testsuite/ld-sh/sh64/relax3.s: Delete. * testsuite/ld-sh/sh64/relax4.s: Delete. * testsuite/ld-sh/sh64/reldl-1.s: Delete. * testsuite/ld-sh/sh64/reldl-2.s: Delete. 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2018-04-16Remove w65 supportAlan Modra1-6/+0
include/ * coff/internal.h: Remove w65 support. * coff/w65.h: Delete. bfd/ * Makefile.am: Remove w65 support. * archures.c: Likewise. * coffcode.h: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * targets.c: Likewise. * coff-w65.c: Delete. * cpu-w65.c: Delete. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. opcodes/ * Makefile.am: Remove w65 support. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Likewise. * w65-dis.c: Delete. * w65-opc.h: Delete. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. binutils/ * testsuite/binutils-all/objcopy.exp: Remove w65 support. ld/ * Makefile.am: Remove w65 support. * configure.tgt: Likewise. * emulparams/w65.sh: Delete. * scripttempl/w65.sc: Delete. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate.
2018-04-16Remove m88k supportAlan Modra1-6/+0
include/ * coff/internal.h: Remove m88k support. * coff/m88k.h: Delete. * opcode/m88k.h: Delete. bfd/ * Makefile.am: Remove m88k support. * aoutx.h: Likewise. * archures.c: Likewise. * coffcode.h: Likewise. * coffswap.h: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * cpu-ns32k.c: Likewise. * elf32-nds32.c: Likewise. * mach-o.c: Likewise. * netbsd-core.c: Likewise. * reloc.c: Likewise. * targets.c: Likewise. * coff-m88k.c: Delete. * cpu-m88k.c: Delete. * elf32-m88k.c: Delete. * hosts/m88kmach3.h: Delete. * m88kmach3.c: Delete. * m88kopenbsd.c: Delete. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. opcodes/ * Makefile.am: Remove m88k support. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Likewise. * m88k-dis.c: Delete. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. binutils/ * MAINTAINERS (Mark Kettenis): Move to past maintainers. * testsuite/binutils-all/objdump.exp: Remove m88k support. gas/ * configure.ac: Remove m88k support. * config.in: Regenerate. * configure: Regenerate. ld/ * Makefile.am: Remove m88k support. * configure.host: Likewise. * configure.tgt: Likewise. * testsuite/ld-elf/sec-to-seg.exp: Likewise. * emulparams/m88kbcs.sh: Delete. * scripttempl/m88kbcs.sc: Delete. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate.
generated by cgit v1.1 at 2024-07-16 20:32:10 +0000