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path: root/opcodes/arc-dis.c
AgeCommit message (Expand)AuthorFilesLines
2024-02-14arc: Put DBNZ instruction to a separate classYuriy Kolerov1-0/+1
2024-01-04Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2023-11-21[opcodes] ARC + PPC: Fix -Walloc-size warningsJan-Benedict Glaw1-1/+1
2023-09-25Revert "arc: Add new opcode functions for ARCv3 ISA."Claudiu Zissulescu1-209/+81
2023-09-25arc: Add new opcode functions for ARCv3 ISA.Claudiu Zissulescu1-81/+209
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2022-09-06opcodes: Add non-enum disassembler optionsTsukasa OI1-0/+2
2022-07-20Re: opcodes/arc: Implement style support in the disassemblerAlan Modra1-1/+1
2022-07-18opcodes/arc: Implement style support in the disassemblerClaudiu Zissulescu1-46/+102
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2021-06-02arc: Construct disassembler options dynamicallyShahab Vahedi1-27/+153
2021-03-31Use bool in opcodesAlan Modra1-55/+55
2021-03-29opcodes int vs bfd_boolean fixesAlan Modra1-1/+1
2021-03-22Add startswith function and use it instead of CONST_STRNEQ.Martin Liska1-1/+1
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-07-14arc: Detect usage of illegal double register pairsClaudiu Zissulescu1-3/+11
2020-07-06Fix spelling mistakes in some of the binutils sub-directories.Nick Clifton1-1/+1
2020-03-26Re: ARC: Use of uninitialised valueAlan Modra1-2/+2
2020-03-22ARC: Use of uninitialised valueAlan Modra1-3/+4
2020-01-13[ARC] [COMMITTED] Change ACCL/ACCH reg name to generic.Claudiu Zissulescu1-1/+1
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-12-11Remove more shifts for sign/zero extensionAlan Modra1-2/+1
2019-12-11ubsan: arc: shift exponent 32 is too large for 32-bit type 'int'Alan Modra1-1/+1
2019-08-07Prevent objdump from aborting when asked to disassemble an unknown type of AR...Phillipe Antoine1-6/+11
2019-07-24[ARC] Update disassembler opcode selectionClaudiu Zissulescu1-1/+23
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-03-03opcodes error messagesAlan Modra1-2/+4
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-11-21[ARC] Improve printing of pc-relative instructions.claziss1-16/+46
2017-11-03[ARC] Force the disassam to use the hexadecimal number for printingclaziss1-1/+13
2017-11-03[ARC] Sync opcode data base.claziss1-0/+1
2017-06-29[ARC] Use FOR_EACH_DISASSEMBLER_OPTION to iterate over optionsAnton Kolesov1-14/+6
2017-06-29[ARC] Fix handling of cpu=... disassembler option valueAnton Kolesov1-8/+8
2017-05-30[ARC] Allow CPU to be enforced via disassemble_info optionsAnton Kolesov1-26/+105
2017-05-10[ARC] Object attributes.Claudiu Zissulescu1-1/+2
2017-04-25[ARC] Enhance enter/leave mnemonics.Claudiu Zissulescu1-3/+16
2017-04-05-Wwrite-strings: Constify struct disassemble_info's disassembler_options fieldPedro Alves1-2/+2
2017-02-06[ARC] Provide an interface to decode ARC instructions.Claudiu Zissulescu1-37/+174
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-11-29[ARC] Add checking for LP_COUNT reg usage, improve error reporting.Claudiu Zissulescu1-1/+3
2016-11-29[ARC] Fix disassembler option.Claudiu Zissulescu1-55/+40
2016-11-03arc: Implement NPS-400 dcmac instructionGraham Markall1-0/+4
2016-11-03arc: Change max instruction length to 64-bitsAndrew Burgess1-282/+189
2016-11-03arc: Swap highbyte and lowbyte in print_insn_arcGraham Markall1-4/+4
2016-11-03arc: Replace ARC_SHORT macro with arc_opcode_len functionGraham Markall1-4/+4
2016-10-14[ARC] Disassembler: fix LIMM detection for short instructions.Claudiu Zissulescu1-2/+3
2016-10-06-Wimplicit-fallthrough warning fixesAlan Modra1-0/+1
2016-09-16[ARC] Disassemble correctly extension instructions.Claudiu Zissulescu1-3/+3
2016-09-14Stop the ARC disassembler from seg-faulting if initialised without a BFD pres...Anton Kolesov1-3/+8
2016-08-30Fixed issue with NULL pointer access on header var.Cupertino Miranda1-1/+4
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