| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2020-04-30 | AArch64: add GAS support for UDF instruction | Alex Coplan | 1 | -1900/+1912 |
| 2020-04-20 | [AArch64, Binutils] Add missing TSB instruction | Sudakshina Das | 1 | -1263/+1265 |
| 2020-04-20 | [AArch64, Binutils] Make hint space instructions valid for Armv8-a | Sudakshina Das | 1 | -1223/+1223 |
| 2020-01-27 | AArch64: Fix cfinv disassembly issues | Tamar Christina | 1 | -1182/+1182 |
| 2020-01-03 | Arm64: correct uzp{1,2} mnemonics | Jan Beulich | 1 | -2/+2 |
| 2020-01-03 | Arm64: correct 64-bit element fmmla encoding | Jan Beulich | 1 | -45/+45 |
| 2020-01-01 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2019-11-07 | [gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X] | Matthew Malcomson | 1 | -49/+50 |
| 2019-11-07 | [binutils][aarch64] Matrix Multiply extension enablement [8/X] | Matthew Malcomson | 1 | -424/+733 |
| 2019-11-07 | [binutils][aarch64] Bfloat16 enablement [2/X] | Matthew Malcomson | 1 | -68/+268 |
| 2019-07-01 | [gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AES | Matthew Malcomson | 1 | -286/+308 |
| 2019-05-09 | [binutils][aarch64] Add SVE2 instructions. | Matthew Malcomson | 1 | -941/+4120 |
| 2019-05-09 | [binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand. | Matthew Malcomson | 1 | -11/+12 |
| 2019-05-09 | [binutils][aarch64] New SVE_Zm4_11_INDEX operand. | Matthew Malcomson | 1 | -7/+8 |
| 2019-05-09 | [binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand. | Matthew Malcomson | 1 | -10/+11 |
| 2019-05-09 | [binutils][aarch64] New SVE_ADDR_ZX operand. | Matthew Malcomson | 1 | -33/+34 |
| 2019-05-09 | [binutils][aarch64] New SVE_Zm3_11_INDEX operand. | Matthew Malcomson | 1 | -7/+8 |
| 2019-05-09 | [binutils][aarch64] Introduce SVE_IMM_ROT3 operand. | Matthew Malcomson | 1 | -19/+20 |
| 2019-05-01 | [BINUTILS, AArch64] Enable Transactional Memory Extension | Sudakshina Das | 1 | -940/+955 |
| 2019-04-11 | [BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions | Sudakshina Das | 1 | -80/+81 |
| 2019-04-11 | [BINUTILS, AArch64, 1/2] Add new LDGM/STGM instruction | Sudakshina Das | 1 | -1231/+1253 |
| 2019-01-25 | AArch64: Add new STZGM instruction for Armv8.5-A Memory Tagging Extension. | Sudi Das | 1 | -1248/+1259 |
| 2019-01-25 | AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte... | Sudi Das | 1 | -1305/+1281 |
| 2019-01-01 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2018-11-12 | [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension | Sudakshina Das | 1 | -1281/+1305 |
| 2018-11-12 | [BINUTILS, AARCH64, 5/8] Add Tag getting instruction in Memory Tagging Extension | Sudakshina Das | 1 | -1275/+1286 |
| 2018-11-12 | [BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten... | Sudakshina Das | 1 | -1416/+1528 |
| 2018-11-12 | [BINUTILS, AARCH64, 3/8] Add Pointer Arithmetic instructions in Memory Taggin... | Sudakshina Das | 1 | -1514/+1538 |
| 2018-11-12 | [BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex... | Sudakshina Das | 1 | -2323/+2351 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction | Sudakshina Das | 1 | -973/+975 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions | Sudakshina Das | 1 | -946/+950 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-A | Sudakshina Das | 1 | -913/+914 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-A | Sudakshina Das | 1 | -2125/+2215 |
| 2018-07-12 | This patch adds support for the SSBB and PSSBB speculation barrier instructio... | Nick Clifton | 1 | -903/+906 |
| 2018-06-29 | Fix AArch64 encodings for by element instructions. | Tamar Christina | 1 | -69/+70 |
| 2018-06-22 | Correct negs aliasing on AArch64. | Tamar Christina | 1 | -3/+3 |
| 2018-05-16 | Fix disassembly mask for vector sdot on AArch64. | Tamar Christina | 1 | -158/+178 |
| 2018-05-15 | Modify AArch64 Assembly and disassembly functions to be able to fail and repo... | Tamar Christina | 1 | -62/+63 |
| 2018-03-28 | Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R... | Nick Clifton | 1 | -515/+548 |
| 2018-01-09 | Add support for the AArch64's CSDB instruction. | James Greenhalgh | 1 | -899/+900 |
| 2018-01-03 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2017-11-16 | Add assembler and disassembler support for the new Armv8.4-a instructions for... | Tamar Christina | 1 | -2924/+3464 |
| 2017-11-09 | Adds the new Fields and Operand types for the new instructions in Armv8.4-a. | Tamar Christina | 1 | -89/+95 |
| 2017-07-24 | [AArch64] Fix the bit pattern order in the comments in auto-generated file | Jiong Wang | 1 | -1686/+1686 |
| 2017-06-28 | [AArch64] Add dot product support for AArch64 to binutils | Tamar Christina | 1 | -179/+203 |
| 2017-02-24 | [AArch64] Additional SVE instructions | Richard Sandiford | 1 | -1856/+2294 |
| 2017-01-02 | Update year range in copyright notice of all files. | Alan Modra | 1 | -1/+1 |
| 2016-12-13 | [Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm field | Renlin Li | 1 | -2/+2 |
| 2016-11-18 | [AArch64] Add ARMv8.3 FCMLA and FCADD instructions | Szabolcs Nagy | 1 | -2121/+2158 |
| 2016-11-18 | [AArch64] Add ARMv8.3 weaker release consistency load instructions | Szabolcs Nagy | 1 | -1151/+1184 |
