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2020-10-26CSKY: Change plsl.u16 to plsl.16.Cooper Qu1-0/+4
2020-10-26CSKY: Fix and add some instructions for VDSPV1.Cooper Qu1-0/+8
2020-10-26Change avxvnni disassembler output from {vex3} to {vex}Cui,Lili1-0/+4
2020-10-22opcodes/po/es.po: Remove the duplicated entryH.J. Lu1-0/+4
2020-10-22Fix printf formatting errors where "0x" is used as a prefix for a decimal num...Dr. David Alan Gilbert1-0/+4
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian1-0/+13
2020-10-16Enhancement for avx-vnni patchCui,Lili1-0/+11
2020-10-14x86: Support Intel AVX VNNIH.J. Lu1-0/+27
2020-10-14x86: Add support for Intel HRESET instructionLili Cui1-0/+21
2020-10-14x86: Support Intel UINTRLili Cui1-0/+23
2020-10-14x86: Remove the prefix byte from non-VEX/EVEX base_opcodeH.J. Lu1-0/+10
2020-10-13x86: Rename VexOpcode to OpcodePrefixH.J. Lu1-0/+17
2020-10-05Fix spelling mistakesSamanta Navarro1-0/+6
2020-10-05x86-64: Always display suffix for %LQ in 64bitH.J. Lu1-0/+5
2020-10-05x86: Clear modrm if not neededH.J. Lu1-0/+7
2020-09-28This patch introduces ETMv4 (Embedded Trace Macrocell) system registers for t...Przemyslaw Wirkus1-3/+20
2020-09-28This patch introduces ETE (Embedded Trace Extension) system registers for the...Przemyslaw Wirkus1-0/+4
2020-09-28This patch introduces TRBE (Trace Buffer Extension) system registers for the ...Przemyslaw Wirkus1-0/+5
2020-09-26ubsan: opcodes/csky-opc.h:929 shift exponent 536870912Alan Modra1-10/+18
2020-09-25Put together MOD_VEX_0F38* in i386-dis.c,Cui,Lili1-0/+5
2020-09-24csky/opcodes: enclose if body in curly bracesAndrew Burgess1-0/+5
2020-09-24Add support for Intel TDX instructions.Cui,Lili1-0/+18
2020-09-23CSKY: Add objdump option -M abi-names.Cooper Qu1-0/+34
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo1-0/+21
2020-09-21rx-dis.c:103:3: suspicious concatenation of string literalsAlan Modra1-0/+8
2020-09-18bpf: xBPF SDIV, SMOD instructionsDavid Faust1-0/+7
2020-09-17opcodes/csky: return the default disassembler when there is no bfdAndrew Burgess1-0/+5
2020-09-16Tidy elf_symbol_fromAlan Modra1-0/+4
2020-09-10Stop symbols generated by the annobin gcc plugin from breaking the disassembl...Nick Clifton1-0/+7
2020-09-10CSKY: Add L2Cache instructions for CK860.Cooper Qu1-0/+6
2020-09-10Fix compile time warnings when building for the CSKY target on a 32-bit host.Nick Clifton1-0/+5
2020-09-10sprintf arg overlaps destinationAlan Modra1-0/+4
2020-09-09CSKY: Change mvtc and mulsw's ISA flag.Cooper Qu1-0/+5
2020-09-09CSKY: Add FPUV3 instructions, which supported by ck860f.Cooper Qu1-0/+24
2020-09-08aarch64: Add support for Armv8-R system registersAlex Coplan1-0/+22
2020-09-08aarch64: Add support for Armv8-R DFB aliasAlex Coplan1-0/+10
2020-09-08aarch64: Add base support for Armv8-RAlex Coplan1-0/+8
2020-09-02ubsan: v850-opc.c:412 left shift cannot be representedAlan Modra1-0/+13
2020-09-02ubsan: i386-dis.cAlan Modra1-0/+6
2020-09-02ubsan: csky-dis.c:1038 left shift cannot be representedAlan Modra1-0/+4
2020-09-02ubsan: crx-dis.c:571 left shift of negative valueAlan Modra1-0/+6
2020-09-02ubsan: *-ibld.cAlan Modra1-0/+18
2020-09-02ubsan: bfin-dis.c:160 shift exponent 32 is too largeAlan Modra1-0/+4
2020-09-02CSKY: Add CPU CK803r3.Cooper Qu1-0/+5
2020-09-02CSKY: Fix Encode of mulsws.Cooper Qu1-0/+4
2020-09-01mep: ubsan: mep-ibld.c:1635,1645,1652 left shift of negative valueAlan Modra1-0/+4
2020-08-31CSKY: Refine operand format error reporting.Cooper Qu1-0/+5
2020-08-30cr16 disassembly error of disp20 fieldsAlan Modra1-0/+9
2020-08-29PR26446 UBSAN: tc-csky.c:2618,4022 index out of boundsAlan Modra1-0/+6
2020-08-28PR26449, PR26450 UBSAN: frv-ibld.c:135 left shiftAlan Modra1-0/+13
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