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AgeCommit message (Expand)AuthorFilesLines
2020-09-192.35.1 point releasebinutils-2_35_1Nick Clifton1-0/+7
2020-08-26opcodes: Add missing entries to ebpf_isa_attrJose E. Marchesi1-0/+4
2020-08-26bpf: add xBPF ISAJose E. Marchesi1-0/+9
2020-08-18PowerPC: Rename xvcvbf16sp to xvcvbf16spnPeter Bergner1-0/+8
2020-08-12Remove spurious text in changelog entryNick Clifton1-0/+4
2020-08-04x86: Add {disp16} pseudo prefixH.J. Lu1-0/+16
2020-07-24Set version to 2.35.0 and enable developmentNick Clifton1-0/+4
2020-07-242.35 Releasebinutils-2_35Nick Clifton1-0/+6
2020-07-24Updated German translation for the opcodes sub-directoryNick Clifton1-0/+4
2020-07-15x86: Don't display eiz with no scaleH.J. Lu1-0/+6
2020-07-15x86-64: Zero-extend lower 32 bits displacement to 64 bitsH.J. Lu1-0/+6
2020-07-06Updated translations for various binutils sub-directoriesNick Clifton1-0/+5
2020-07-04Set version to 2.34.90 and regenerate filesNick Clifton1-0/+5
2020-07-04Add markers for binutils 2.35 branchNick Clifton1-0/+4
2020-07-02x86: Add SwapSourcesH.J. Lu1-0/+9
2020-06-30RISC-V: Support debug and float CSR as the unprivileged ones.Nelson Chu1-0/+5
2020-06-29C++ commentsAlan Modra1-0/+10
2020-06-26i386-opc.tbl: Add a blank lineH.J. Lu1-0/+4
2020-06-26x86: Correct VexSIB128 to VecSIB128H.J. Lu1-2/+2
2020-06-26x86: Rename VecSIB to SIB for Intel AMXH.J. Lu1-0/+18
2020-06-26x86: make I disassembler macro available for new useJan Beulich1-0/+7
2020-06-26x86: fix processing of -M disassembler optionJan Beulich1-0/+5
2020-06-25x86: make J disassembler macro available for new useJan Beulich1-0/+6
2020-06-25x86: drop left-over 4-way alternative disassembler templatesJan Beulich1-0/+4
2020-06-25x86: fix SYSRET disassembly, improve {,V}CVTSI2S{S,D} and PTWRITEJan Beulich1-0/+6
2020-06-22RISC-V: Report warning when linking the objects with different priv specs.Nelson Chu1-0/+5
2020-06-18x86: also test alternative VMGEXIT encodingJan Beulich1-0/+4
2020-06-17x86: Delete incorrect vmgexit entry in prefix_tableCui,Lili1-0/+4
2020-06-14x86: Correct xsusldtrk mnemonicH.J. Lu1-0/+7
2020-06-12RISC-V: Drop the privileged spec v1.9 support.Nelson Chu1-0/+4
2020-06-11[PATCH]: aarch64: Refactor representation of system registersAlex Coplan1-0/+23
2020-06-09i386-dis.c: Fix a typo in commentsH.J. Lu1-0/+4
2020-06-09x86: consistently print prefixes explicitly which are invalid with VEX etcJan Beulich1-0/+8
2020-06-09x86: fix {,V}MOV{L,H}PD disassemblyJan Beulich1-0/+15
2020-06-09x86: utilize X macro in EVEX decodingJan Beulich1-0/+60
2020-06-09x86: correct decoding of packed-FP-only AVX encodingsJan Beulich1-0/+10
2020-06-09x86: correct mis-named MOD_0F51 enumeratorJan Beulich1-0/+5
2020-06-08[PATCH] arm: Add DFB instruction for ARMv8-RAlex Coplan1-0/+5
2020-06-08x86: restrict use of register aliasesJan Beulich1-0/+4
2020-06-06Power10 tidiesAlan Modra1-0/+4
2020-06-05bpf stack smashing detectedAlan Modra1-0/+5
2020-06-04cpu,gas,opcodes: remove no longer needed workaround from the BPF portJose E. Marchesi1-0/+8
2020-06-04opcodes: discriminate endianness and insn-endianness in CGEN portsJose E. Marchesi1-0/+43
2020-06-04opcodes: support insn endianness in cgen_cpu_openJose E. Marchesi1-0/+33
2020-06-03Updated Serbian translation for the opcodes sub-directoryNick Clifton1-0/+4
2020-06-03RISC-V: Fix the error when building RISC-V linux native gdbserver.Nelson Chu1-0/+5
2020-06-01Regen opcodes/bpf-desc.cAlan Modra1-0/+4
2020-05-28cpu,opcodes: add instruction semantics to bpf.cpu and minor fixesJose E. Marchesi1-0/+8
2020-05-28ubsan: nios2: undefined shiftAlan Modra1-0/+5
2020-05-28asan: ns32k: use of uninitialized valueAlan Modra1-0/+6
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