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AgeCommit message (Expand)AuthorFilesLines
2022-07-19[AArch64] Support AArch64 MTE memory tag dumps in core filesLuis Machado1-0/+3
2022-07-12LTO plugin: sync header file with GCCMartin Liska1-0/+33
2022-07-08Add markers for 2.39 branchNick Clifton1-0/+4
2022-07-07RISC-V: Added Zfhmin and Zhinxmin.Tsukasa OI1-3/+4
2022-06-29opcodes/aarch64: split off creation of comment text in disassemblerAndrew Burgess1-1/+1
2022-06-28RISC-V: Add 'Sstc' extension and its CSRsTsukasa OI1-0/+10
2022-06-28RISC-V: Add 'Sscofpmf' extension with its CSRsTsukasa OI1-0/+62
2022-06-28RISC-V: Add 'Smstateen' extension and its CSRsTsukasa OI1-0/+42
2022-06-27drop XC16x bitsJan Beulich1-40/+0
2022-06-22RISC-V: Use single h extension to control hypervisor CSRs and instructions.Nelson Chu2-25/+26
2022-06-15[gdb/build] Fix build for gcc < 11Tom de Vries1-0/+2
2022-06-08HOWTO size encodingAlan Modra1-69/+69
2022-05-31Import libiberty from gccAlan Modra2-42/+8
2022-05-30RISC-V: Add zhinx extension supports.jiawei1-2/+3
2022-05-27Replace bfd_hostptr_t with uintptr_tAlan Modra1-6/+6
2022-05-27Remove use of bfd_uint64_t and similarAlan Modra3-33/+33
2022-05-25ppc: extend opindex to 16 bitsDmitry Selyutin1-1/+7
2022-05-23ld: use definitions in generate_reloc rather than raw literalsMark Harmstone1-0/+16
2022-05-20RISC-V: Remove RV128-only fmv instructionsTsukasa OI1-6/+0
2022-05-20Tidy warn-execstack handlingAlan Modra1-6/+3
2022-05-18AArch64: Enable FP16 by default for Armv9-A.Tamar Christina1-0/+1
2022-05-17RISC-V: Added half-precision floating-point v1.0 instructions.Nelson Chu2-0/+77
2022-05-13Import libiberty from gccAlan Modra3-27/+9
2022-05-10include: remove use of PTRAlan Modra1-2/+2
2022-05-09ansidecl.h: sync from GCCMartin Liska1-20/+3
2022-05-04LTO: Handle __real_SYM reference in IRH.J. Lu1-0/+3
2022-05-04gdb: Workaround stringop-overread warning in debuginfod-support.c on s390xMark Wielaard1-0/+7
2022-05-04LTO plugin: sync header file with GCCMartin Liska1-34/+34
2022-05-03Add a linker warning when creating potentially dangerous executable segments....Nick Clifton1-2/+17
2022-04-28libctf: add a comment explaining how to use ctf_*openNick Alcock1-1/+7
2022-04-22RISC-V: Add missing DECLARE_INSNs for Zicbo{m,p,z}Christoph Muellner1-0/+9
2022-04-20Stubs (added in a later patch) will generate new .loader symbols, once the al...Cl?ment Chigot2-0/+12
2022-04-20Add linker warning for when it creates an executable stack.Nick Clifton1-0/+4
2022-04-07Recognize the NT_ARM_SYSTEM_CALL register setLuis Machado1-0/+2
2022-04-07Add support for COFF secidx relocationsMark Harmstone3-0/+7
2022-04-04objdump/opcodes: add syntax highlighting to disassembler outputAndrew Burgess1-5/+83
2022-04-02gdb: rename floatformats_ia64_quad to floatformats_ieee_quadTiezhu Yang1-3/+3
2022-04-01Recognize FreeBSD core dump note for x86 segment base registers.John Baldwin2-0/+5
2022-03-23include, libctf, ld: extend variable section to contain functions tooNick Alcock1-4/+4
2022-03-20LoongArch: Update ABI eflag in elf header.liuzhensong1-14/+23
2022-03-20gas:LoongArch: Fix segment error in compilation due to too long symbol name.liuzhensong1-2/+2
2022-03-18RISC-V: Cache management instructionsTsukasa OI2-0/+11
2022-03-18RISC-V: Prefetch hint instructions and operand setTsukasa OI2-0/+8
2022-03-16binutils/readelf: handle AMDGPU relocation typesSimon Marchi2-0/+25
2022-03-16binutils/readelf: handle NT_AMDGPU_METADATA note nameSimon Marchi2-0/+8
2022-03-16binutils/readelf: decode AMDGPU-specific e_flagsSimon Marchi2-0/+59
2022-03-16binutils/readelf: handle AMDGPU OS ABIsSimon Marchi2-0/+7
2022-03-16bfd: add AMDGCN architectureSimon Marchi3-0/+42
2022-03-16Delete PowerPC macro insn supportAlan Modra1-26/+0
2022-03-16PowerPC64 extended instructions in powerpc_macrosAlan Modra1-3/+5
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