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2024-01-26Backport commits 969f5c0e1 (LoongArch: gas: Add support for s9 register) and ...mengqinggang1-0/+1
2024-01-23aarch64: Include +predres2 in -march=armv8.9-aAndrew Carlotti1-2/+2
2024-01-17Import gcc commit 65388b28656d65595bdaf191df85af81c35ca63 which adds support ...Nick Clifton1-0/+2
2024-01-15Add markers for 2.42 branchNick Clifton1-0/+4
2024-01-15aarch64: rcpc3: Add integer load/store insnsVictor Do Nascimento1-0/+1
2024-01-15aarch64: rcpc3: New RCPC3_ADDR operand typesVictor Do Nascimento1-0/+5
2024-01-15aarch64: rcpc3: Define address operand fields and inserter/extractorsVictor Do Nascimento1-2/+4
2024-01-15aarch64: rcpc3: Create implicit load/store size calc functionVictor Do Nascimento1-0/+3
2024-01-15aarch64: rcpc3: Add +rcpc3 architectural feature support flagVictor Do Nascimento1-0/+2
2024-01-15aarch64: Refactor aarch64_sys_ins_reg_supported_pAndrew Carlotti1-1/+5
2024-01-15aarch64: Remove unused BTI feature bitAndrew Carlotti1-3/+0
2024-01-15aarch64: Add SVE2.1 Contiguous load/store instructions.Srinath Parvathaneni1-0/+3
2024-01-15aarch64: Add SVE2.1 dupq, eorqv and extq instructions.Srinath Parvathaneni1-1/+4
2024-01-15aarch64: Add support for FEAT_SVE2p1.Srinath Parvathaneni1-2/+8
2024-01-15aarch64: Add support for FEAT_SME2p1 instructions.Srinath Parvathaneni1-0/+11
2024-01-15aarch64: Add support for FEAT_B16B16 instructions.Srinath Parvathaneni1-0/+2
2024-01-12aarch64: Add +xs flag for existing instructionsAndrew Carlotti1-0/+3
2024-01-12aarch64: Add +wfxt flag for existing instructionsAndrew Carlotti1-0/+3
2024-01-12aarch64: Add +rcpc2 flag for existing instructionsAndrew Carlotti1-0/+3
2024-01-12aarch64: Add +jscvt flag for existing fjcvtzs instructionAndrew Carlotti1-1/+4
2024-01-10gas: aarch64: Add system registers for Debug and PMU extensionsSaurabh Jha1-0/+15
2024-01-09Synchronize sourceware version of the libiberty sources with the master gcc v...Nick Clifton1-0/+4
2024-01-09aarch64: ADD FEAT_THE RCWCAS instructions.Srinath Parvathaneni1-0/+1
2024-01-09aarch64: Add support for 128-bit system register mrrs and msrr insnsVictor Do Nascimento1-0/+2
2024-01-09aarch64: Implement TLBIP 128-bit instructionVictor Do Nascimento1-0/+1
2024-01-09aarch64: Apply narrowing of allowed immediate values for SYSPVictor Do Nascimento1-1/+6
2024-01-09aarch64: Add support for optional operand pairsVictor Do Nascimento1-1/+11
2024-01-09aarch64: Add support for xzr register in register pair operandsVictor Do Nascimento1-0/+1
2024-01-09aarch64: Expand maximum number of operands from 5 to 6Victor Do Nascimento1-1/+1
2024-01-09aarch64: Add +d128 architectural feature supportVictor Do Nascimento1-0/+3
2024-01-08arm: Add support for Armv8.9-A and Armv9.4-Asrinath1-0/+2
2024-01-05RISC-V: T-HEAD: Fix wrong instruction encoding for th.vsetvliJin Ma1-0/+11
2024-01-04Update year range in copyright notice of binutils filesAlan Modra319-319/+319
2023-12-29LoongArch: include: Add support for tls le relax.changjiachen1-0/+12
2023-12-28x86-64: Add R_X86_64_CODE_4_GOTTPOFF/R_X86_64_CODE_4_GOTPC32_TLSDESCH.J. Lu1-0/+6
2023-12-28x86-64: Add R_X86_64_CODE_4_GOTPCRELXH.J. Lu1-1/+5
2023-12-28x86: Add NT_X86_SHSTK noteSchimpe, Christina1-0/+3
2023-12-28Support APX GPR32 with rex2 prefixCui, Lili1-0/+4
2023-12-25LoongArch: Add support for TLS LD/GD/DESC relaxationmengqinggang1-0/+4
2023-12-25LoongArch: Add tls transition support.Lulu Cai1-0/+6
2023-12-25LoongArch: Add new relocs and macro for TLSDESC.Lulu Cai1-1/+21
2023-12-20s390: Optionally print instruction description in disassemblyJens Remus1-1/+4
2023-12-19aarch64: Add FEAT_ITE supportAndrea Corallo1-0/+2
2023-12-19aarch64: Add FEAT_SPECRES2 supportAndrea Corallo1-1/+4
2023-12-18LoongArch: Add new relocation R_LARCH_CALL36mengqinggang1-0/+2
2023-12-14RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.Jin Ma1-4/+4
2023-12-10Add some new DW_IDX_* constantsTom Tromey1-0/+9
2023-12-05Add basic support for RISC-V 64-bit EFI objectsAndreas Schwab2-0/+66
2023-12-04s390: Support for jump visualization in disassemblyJens Remus1-3/+22
2023-12-01RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0Nelson Chu2-0/+64
generated by cgit v1.1 at 2024-11-14 22:38:47 +0000