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path: root/include/opcode/aarch64.h
AgeCommit message (Expand)AuthorFilesLines
2023-10-04aarch64: system register aliasing detectionVictor Do Nascimento1-0/+1
2023-09-26aarch64: Allow feature flags to occupy >64 bitsRichard Sandiford1-23/+39
2023-09-26aarch64: Restructure feature flag handlingRichard Sandiford1-151/+268
2023-08-22aarch64: Improve naming conventions for A and R-profile architectureVictor Do Nascimento1-54/+54
2023-03-30aarch64: Remove stray reglist variableRichard Sandiford1-1/+1
2023-03-30aarch64: Add the RPRFM instructionRichard Sandiford1-0/+2
2023-03-30aarch64: Add new SVE dot-product instructionsRichard Sandiford1-1/+2
2023-03-30aarch64: Add the SME2 shift instructionsRichard Sandiford1-0/+3
2023-03-30aarch64: Add the SME2 saturating conversion instructionsRichard Sandiford1-0/+1
2023-03-30aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford1-0/+5
2023-03-30aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford1-0/+4
2023-03-30aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford1-0/+2
2023-03-30aarch64: Add the SME2 maximum/minimum instructionsRichard Sandiford1-0/+1
2023-03-30aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford1-0/+3
2023-03-30aarch64: Add the SME2 ZT0 instructionsRichard Sandiford1-0/+11
2023-03-30aarch64: Add the SME2 predicate-related instructionsRichard Sandiford1-0/+11
2023-03-30aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford1-0/+3
2023-03-30aarch64: Add the SME2 MOVA instructionsRichard Sandiford1-0/+10
2023-03-30aarch64: Add support for predicate-as-counter registersRichard Sandiford1-0/+5
2023-03-30aarch64; Add support for vector offset rangesRichard Sandiford1-4/+19
2023-03-30aarch64: Add support for vgx2 and vgx4Richard Sandiford1-0/+13
2023-03-30aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayRichard Sandiford1-3/+3
2023-03-30aarch64: Add +sme2Richard Sandiford1-0/+1
2023-03-30aarch64: Add support for strided register listsRichard Sandiford1-12/+26
2023-03-30aarch64: Add a aarch64_cpu_supports_inst_p helperRichard Sandiford1-0/+3
2023-03-30aarch64: Add an operand class for SVE register listsRichard Sandiford1-0/+1
2023-03-30aarch64: Add an error code for out-of-range registersRichard Sandiford1-1/+9
2023-03-30aarch64: Deprioritise AARCH64_OPDE_REG_LISTRichard Sandiford1-5/+9
2023-03-30aarch64: Update operand_mismatch_kind_namesRichard Sandiford1-1/+4
2023-03-30aarch64: Move ZA range checks to aarch64-opc.cRichard Sandiford1-0/+1
2023-03-30aarch64: Make indexed_za use 64-bit immediatesRichard Sandiford1-1/+1
2023-03-30aarch64: Rename za_tile_vector to za_indexRichard Sandiford1-10/+13
2023-03-30aarch64: Make SME instructions use F_STRICTRichard Sandiford1-0/+2
2023-03-30aarch64: Add sme-i16i64 and sme-f64f64 aliasesRichard Sandiford1-2/+2
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2022-11-14aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira1-1/+5
2022-07-29libopcodes/aarch64: add support for disassembler stylingAndrew Burgess1-1/+27
2022-06-29opcodes/aarch64: split off creation of comment text in disassemblerAndrew Burgess1-1/+1
2022-05-18AArch64: Enable FP16 by default for Armv9-A.Tamar Christina1-0/+1
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2021-12-16aarch64: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford1-40/+62
2021-12-02aarch64: Add BC instructionRichard Sandiford1-1/+3
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford1-7/+25
2021-12-02aarch64: Add support for +mopsRichard Sandiford1-1/+6
2021-12-02aarch64: Add support for Armv8.8-ARichard Sandiford1-0/+3
2021-12-02aarch64: Tweak insn sequence codeRichard Sandiford1-7/+5
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus1-0/+1
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus1-0/+3
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus1-1/+11
2021-11-17aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus1-0/+1
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