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2022-11-02x86: simplify expressions in update_imm()Jan Beulich1-23/+14
2022-11-02RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment.Nelson Chu4-38/+67
2022-11-02Support Intel MSRLISTHu, Lin19-1/+47
2022-11-02Support Intel WRMSRNSHu, Lin19-1/+44
2022-11-02Add handler for more i386_cpu_flagsKong Lingling1-0/+17
2022-11-02Support Intel CMPccXADDHaochen Jiang9-1/+818
2022-11-02Support Intel AVX-VNNI-INT8Cui,Lili10-1/+547
2022-11-02Support Intel AVX-IFMAHongyu Wang15-15/+252
2022-11-01opcodes/arm: use '@' consistently for the comment characterAndrew Burgess121-2291/+2291
2022-10-31x86: minor improvements to optimize_imm() (part III)Jan Beulich1-9/+8
2022-10-31x86: Silence GCC 12 warning on tc-i386.cH.J. Lu2-5/+5
2022-10-31Support Intel PREFETCHICui, Lili13-3/+103
2022-10-31RX assembler: switch arguments of thw MVTACGU insn.Yoshinori Sato2-4/+8
2022-10-29RISC-V: Always generate mapping symbols at the start of the sections.Nelson Chu3-41/+0
2022-10-28gas: NEWS: Note support for RISC-V ZawrsPalmer Dabbelt1-0/+2
2022-10-28gas: NEWS: Add a missing newlinePalmer Dabbelt1-0/+1
2022-10-28RISC-V: Improve "bits undefined" diagnosticsTsukasa OI1-2/+2
2022-10-28RISC-V: Fallback for instructions longer than 64bTsukasa OI1-5/+8
2022-10-28RISC-V/gas: fix build with certain gcc versionsJan Beulich1-7/+7
2022-10-28RISC-V: Fix build failure for -Werror=maybe-uninitializedTsukasa OI1-1/+1
2022-10-28RISC-V: Output mapping symbols with ISA string.Nelson Chu24-328/+404
2022-10-27PowerPC: Add support for RFC02658 - MMA+ Outer-Product InstructionsPeter Bergner4-2/+81
2022-10-27PowerPC: Add support for RFC02653 - Dense Math FacilityPeter Bergner6-65/+270
2022-10-27re: Support Intel AMX-FP16Alan Modra2-0/+2
2022-10-24x86: consolidate VPCLMUL testsJan Beulich15-268/+156
2022-10-24x86: consolidate VAES testsJan Beulich15-352/+211
2022-10-24x86: emit {evex} prefix when disassembling ambiguous AVX512VL insnsJan Beulich31-361/+361
2022-10-21Support Intel AMX-FP16Cui,Lili9-1/+97
2022-10-20x86: Check VEX/EVEX encoding before checking vector operandsH.J. Lu5-4/+8
2022-10-20x86: re-work AVX-VNNI supportJan Beulich7-12/+36
2022-10-19aarch64-pe support for LD, GAS and BFDJedidiah Thompson8-25/+108
2022-10-18x86: generalize gas documentation for disabling of ISA extensionsJan Beulich1-49/+5
2022-10-17Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp}CaiJingtao5-205/+566
2022-10-16PowerPC se_rfmci and VLE, SPE2 and LSP insns with -manyAlan Modra5-56/+55
2022-10-14PowerPC SPE disassembly and testsAlan Modra4-14/+11
2022-10-14e200 LSP supportAlan Modra5-12/+38
2022-10-14RISC-V: Imply 'Zicsr' from privileged extensions with CSRsTsukasa OI1-0/+6
2022-10-14RISC-V: Test DWARF register number for "fp"Tsukasa OI2-0/+4
2022-10-12x86: drop "regmask" static variableJan Beulich1-3/+2
2022-10-11Re: Error: attempt to get value of unresolved symbol `L0'Nick Clifton4-10/+26
2022-10-11add --enable-default-compressed-debug-sections-algorithm configure optionMartin Liska5-3/+40
2022-10-11refactor usage of compressed_debug_section_typeMartin Liska1-25/+9
2022-10-11Error: attempt to get value of unresolved symbol `L0'Nick Clifton2-2/+12
2022-10-05x86/gas: support quoted address scale factor in AT&T syntaxJan Beulich4-12/+35
2022-10-05Arm64: support CLEARBHB aliasJan Beulich2-1/+3
2022-10-04gas: NEWS: Mention the T-Head extensions that were recently addedPalmer Dabbelt1-0/+5
2022-10-04Re: compress .gnu.debuglto_.debug_* sections if requestedAlan Modra1-13/+7
2022-10-04compress .gnu.debuglto_.debug_* sections if requestedMartin Liska1-1/+3
2022-10-04RISC-V/gas: allow generating up to 176-bit instructions with .insnJan Beulich7-10/+82
2022-10-04RISC-V/gas: don't open-code insn_length()Jan Beulich1-1/+1