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2022-01-23Regenerate Makefile.in files with automake 1.15.1H.J. Lu1-1/+0
2022-01-23Regenerate configure files with autoconf 2.69H.J. Lu1-15/+3
2022-01-22Change version number to 2.38.50 and regenerate filesNick Clifton3-23/+40
2022-01-22Add markers for 2.38 branchNick Clifton2-0/+6
2022-01-22RISC-V: create new frag after alignment.Lifang Xia1-0/+6
2022-01-21drop old unused stamp-h.in fileMike Frysinger1-1/+0
2022-01-17Update the config.guess and config.sub files from the master repository and r...Nick Clifton3-1800/+2149
2022-01-17Fix Z80 assembly failure.Sergey Belyashov2-0/+7
2022-01-13Re: gas: add visibility support using GNU syntax on XCOFFAlan Modra1-1/+1
2022-01-12gas: add visibility support using GNU syntax on XCOFFClément Chigot5-0/+85
2022-01-12gas: add visibility support for XCOFFClément Chigot7-36/+405
2022-01-12objdump, readelf: Emit "CU:" format only when wide output is requestedHans-Peter Nilsson1-1/+1
2022-01-11gas/doc: mention quoted symbol namesJan Beulich1-1/+4
2022-01-10XCOFF: add support for TLS relocations on hidden symbolsClément Chigot8-97/+308
2022-01-07RISC-V: update docs to reflect privileged spec v1.9 has been droppedPhilipp Tomsich5-8/+8
2022-01-07RISC-V: update docs for -mpriv-spec/--with-priv-spec for 1.12Philipp Tomsich6-9/+9
2022-01-07RISC-V: Updated the default ISA spec to 20191213.Nelson Chu7-7/+7
2022-01-06aarch64: Add support for new SME instructionsRichard Sandiford2-0/+56
2022-01-06x86: drop NoAVX insn attributeJan Beulich1-17/+21
2022-01-06x86-64: restrict PC32 -> PLT32 conversionJan Beulich2-3/+7
2022-01-05Adjust quoted-sym-names testAlan Modra2-6/+6
2022-01-04x86/Intel: correct VFPCLASSP{S,D} handling when displacement is presentJan Beulich4-5/+9
2022-01-04gas: rework handling of backslashes in quoted symbol namesJan Beulich5-15/+69
2022-01-02Update year range in copyright notice of binutils filesAlan Modra575-579/+579
2022-01-01ubsan: next_char_of_string signed integer overflowAlan Modra1-2/+2
2022-01-01ubsan: signed integer multiply overflowAlan Modra1-1/+6
2021-12-28gas reloc sortingAlan Modra4-42/+30
2021-12-24RISC-V: Rewrite the csr testcases.Nelson Chu42-1521/+3567
2021-12-24RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta5-5/+313
2021-12-24RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/testsVineet Gupta9-90/+0
2021-12-22RISC-V: Update Scalar Crypto testcases.jiawei18-144/+144
2021-12-21x86: -mfence-as-lock-add=yes doesn't work for 16-bit modeJan Beulich1-1/+6
2021-12-21gas/ELF: avoid below-base ref in obj_elf_parse_section_letters()Jan Beulich1-13/+11
2021-12-17x86: Terminate mnemonicendp in swap_operand()Vladimir Mezentsev8-420/+420
2021-12-16Fix AVR assembler so that it creates relocs that will work with linker relaxa...Nick Clifton7-6/+45
2021-12-16arm: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford11-3/+94
2021-12-16arm: Add support for Armv8.7-A and Armv8.8-ARichard Sandiford9-1/+65
2021-12-16aarch64: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford18-2/+95
2021-12-16RISC-V: Support svinval extension with frozen version 1.0.Nelson Chu2-0/+20
2021-12-15loongarch64 build failure on 32-bit hostAlan Modra1-6/+6
2021-12-09RISC-V: Clarify the behavior of .option arch directive.Nelson Chu8-9/+13
2021-12-02aarch64: Update gas/NEWS for recent changesRichard Sandiford1-1/+4
2021-12-02aarch64: Add BC instructionRichard Sandiford7-0/+90
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford4-10/+202
2021-12-02aarch64: Add support for +mopsRichard Sandiford7-0/+1592
2021-12-02aarch64: Add Armv8.8-A system registersRichard Sandiford5-0/+46
2021-12-02aarch64: Add id_aa64isar2_el1Richard Sandiford5-0/+8
2021-12-02aarch64: Add support for Armv8.8-ARichard Sandiford4-2/+10
2021-12-02aarch64: Provide line info for unclosed sequencesRichard Sandiford5-15/+17
2021-12-02aarch64: Add maximum immediate value to aarch64_sys_regRichard Sandiford9-39/+66
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