| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-06-05 | arm: minor documentation cleanup given removal of FPA | Richard Earnshaw | 1 | -3/+0 |
| 2024-06-05 | arm: remove disassembly support for the FPA co-processor | Richard Earnshaw | 2 | -6/+6 |
| 2024-06-05 | arm: remove FPA instructions from assembler | Richard Earnshaw | 1 | -699/+0 |
| 2024-06-05 | arm: remove options to select the FPA | Richard Earnshaw | 2 | -23/+2 |
| 2024-06-05 | arm: change default FPUs from FPA to none | Richard Earnshaw | 1 | -62/+63 |
| 2024-06-05 | arm: redirect fp constant data directives through a wrapper | Richard Earnshaw | 12 | -10/+55 |
| 2024-06-05 | arm: adjust FPU selection logic | Richard Earnshaw | 1 | -9/+2 |
| 2024-06-05 | arm: default to softvfp on armv6 or later cores | Richard Earnshaw | 1 | -17/+17 |
| 2024-06-05 | arm: rename FPU_ARCH_VFP to FPU_ARCH_SOFTVFP | Richard Earnshaw | 5 | -58/+96 |
| 2024-06-05 | arm: remove FPA related tests | Richard Earnshaw | 27 | -1858/+119 |
| 2024-06-05 | RISC-V: Tidy vendor core-v extension gas testcases | Nelson Chu | 146 | -1629/+1393 |
| 2024-06-05 | RISC-V: Add support for XCVmem extension in CV32E40P | Mary Bennett | 68 | -0/+730 |
| 2024-06-05 | RISC-V: Add support for XCVbi extension in CV32E40P | Mary Bennett | 19 | -1/+102 |
| 2024-06-05 | RISC-V: Add support for XCVelw extension in CV32E40P | Mary Bennett | 10 | -0/+191 |
| 2024-06-04 | LoongArch: Make align symbol be in same section with alignment directive | mengqinggang | 5 | -4/+103 |
| 2024-06-04 | arm: testsuite: fix msdos line endings in tests | Richard Earnshaw | 2 | -18/+18 |
| 2024-05-31 | aarch64, testsuite: avoid regexes in opcode field | Claudio Bantaloukas | 2 | -493/+493 |
| 2024-05-31 | gas, aarch64: Fixes in texi and tests following faminmax and lut changes | saurabh.jha@arm.com | 4 | -162/+162 |
| 2024-05-31 | x86: reduce check_{byte,word,long,qword}_reg() overhead | Jan Beulich | 1 | -4/+15 |
| 2024-05-29 | x86/Intel: warn about undue mnemonic suffixes | Jan Beulich | 33 | -157/+117 |
| 2024-05-29 | x86/Intel: SHLD/SHRD have dual meaning | Jan Beulich | 4 | -2/+79 |
| 2024-05-29 | PR31796, Internal error in write_function_pdata at obj-coff-seh | Alan Modra | 1 | -2/+22 |
| 2024-05-28 | gas, aarch64: Add SVE2 lut extension | saurabh.jha@arm.com | 9 | -1/+464 |
| 2024-05-28 | gas, aarch64: Add AdvSIMD lut extension | saurabh.jha@arm.com | 10 | -0/+499 |
| 2024-05-28 | Fix typo in assembler documentation | Nick Clifton | 1 | -1/+1 |
| 2024-05-28 | Fix: internal error in write_function_pdata at obj-coff-seh | Nick Clifton | 1 | -0/+5 |
| 2024-05-28 | RISC-V: Fix U insn; replace opcode6 with opcode7 in gas/doc/c-riscv.texi | Javier Mora | 1 | -22/+22 |
| 2024-05-24 | Re: LoongArch: gas: Adjust DWARF CIE alignment factors | Alan Modra | 1 | -22/+22 |
| 2024-05-24 | gas: extend \+ support to .irp / .irpc | Jan Beulich | 6 | -23/+24 |
| 2024-05-24 | gas: adjust handling of quotes for .irpc | Jan Beulich | 5 | -21/+40 |
| 2024-05-24 | x86: simplify VexVVVV_SRC2 handling for the XOP case | Jan Beulich | 1 | -9/+5 |
| 2024-05-24 | x86: simplify / consolidate check_{word,long,qword}_reg() | Jan Beulich | 1 | -16/+4 |
| 2024-05-24 | x86: correct VCVT{,U}SI2SD | Jan Beulich | 3 | -5/+56 |
| 2024-05-22 | restore build with --enable-maintainer-mode | Indu Bhagat | 3 | -3/+0 |
| 2024-05-22 | aarch64: fix incorrect encoding for system register pmsdsfr_el1 | Matthieu Longo | 1 | -2/+2 |
| 2024-05-22 | Support APX zero-upper | Cui, Lili | 7 | -2/+288 |
| 2024-05-22 | X86: Remove "i.rex" to eliminate extra conditional branch | Cui, Lili | 1 | -1/+1 |
| 2024-05-22 | Add check for 8-bit old registers in EVEX format | Cui, Lili | 3 | -3/+9 |
| 2024-05-22 | x86: Split REX/REX2 old registers judgment. | Cui, Lili | 1 | -16/+14 |
| 2024-05-21 | gas: ginsn: remove unnecessary buffer allocation and free | Indu Bhagat | 1 | -15/+12 |
| 2024-05-21 | gas: drop remnants of ia64-*-aix* | Jan Beulich | 2 | -24/+0 |
| 2024-05-20 | aarch64: Add support for the fpmr system register | Claudio Bantaloukas | 4 | -0/+23 |
| 2024-05-20 | RISC-V: PR31733, Change initial CFI operation from DW_CFA_def_cfa_register to... | Sung-hun Kim | 1 | -1/+1 |
| 2024-05-17 | aarch64: correct SVE2.1 ld2q (scalar plus scalar) | Jan Beulich | 1 | -1/+1 |
| 2024-05-17 | aarch64: correct SVE2.1 ld{3,4}q / st{3,4}q (scalar plus immediate) | Jan Beulich | 3 | -13/+13 |
| 2024-05-17 | LoongArch: gas: Adjust DWARF CIE alignment factors | mengqinggang | 1 | -5/+9 |
| 2024-05-16 | gas: sframe: fix typo to use FP instead of BP | Indu Bhagat | 1 | -4/+4 |
| 2024-05-16 | aarch64: fp8 convert and scale - add sme2 insn variants | Victor Do Nascimento | 6 | -2/+623 |
| 2024-05-16 | aarch64: fp8 convert and scale - add sve2 insn variants | Victor Do Nascimento | 7 | -0/+313 |
| 2024-05-16 | aarch64: fp8 convert and scale - Add advsimd insn variants | Victor Do Nascimento | 5 | -0/+581 |
