Age | Commit message (Expand) | Author | Files | Lines |
2022-11-02 | x86: simplify expressions in update_imm() | Jan Beulich | 1 | -23/+14 |
2022-11-02 | RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment. | Nelson Chu | 4 | -38/+67 |
2022-11-02 | Support Intel MSRLIST | Hu, Lin1 | 9 | -1/+47 |
2022-11-02 | Support Intel WRMSRNS | Hu, Lin1 | 9 | -1/+44 |
2022-11-02 | Add handler for more i386_cpu_flags | Kong Lingling | 1 | -0/+17 |
2022-11-02 | Support Intel CMPccXADD | Haochen Jiang | 9 | -1/+818 |
2022-11-02 | Support Intel AVX-VNNI-INT8 | Cui,Lili | 10 | -1/+547 |
2022-11-02 | Support Intel AVX-IFMA | Hongyu Wang | 15 | -15/+252 |
2022-11-01 | opcodes/arm: use '@' consistently for the comment character | Andrew Burgess | 121 | -2291/+2291 |
2022-10-31 | x86: minor improvements to optimize_imm() (part III) | Jan Beulich | 1 | -9/+8 |
2022-10-31 | x86: Silence GCC 12 warning on tc-i386.c | H.J. Lu | 2 | -5/+5 |
2022-10-31 | Support Intel PREFETCHI | Cui, Lili | 13 | -3/+103 |
2022-10-31 | RX assembler: switch arguments of thw MVTACGU insn. | Yoshinori Sato | 2 | -4/+8 |
2022-10-29 | RISC-V: Always generate mapping symbols at the start of the sections. | Nelson Chu | 3 | -41/+0 |
2022-10-28 | gas: NEWS: Note support for RISC-V Zawrs | Palmer Dabbelt | 1 | -0/+2 |
2022-10-28 | gas: NEWS: Add a missing newline | Palmer Dabbelt | 1 | -0/+1 |
2022-10-28 | RISC-V: Improve "bits undefined" diagnostics | Tsukasa OI | 1 | -2/+2 |
2022-10-28 | RISC-V: Fallback for instructions longer than 64b | Tsukasa OI | 1 | -5/+8 |
2022-10-28 | RISC-V/gas: fix build with certain gcc versions | Jan Beulich | 1 | -7/+7 |
2022-10-28 | RISC-V: Fix build failure for -Werror=maybe-uninitialized | Tsukasa OI | 1 | -1/+1 |
2022-10-28 | RISC-V: Output mapping symbols with ISA string. | Nelson Chu | 24 | -328/+404 |
2022-10-27 | PowerPC: Add support for RFC02658 - MMA+ Outer-Product Instructions | Peter Bergner | 4 | -2/+81 |
2022-10-27 | PowerPC: Add support for RFC02653 - Dense Math Facility | Peter Bergner | 6 | -65/+270 |
2022-10-27 | re: Support Intel AMX-FP16 | Alan Modra | 2 | -0/+2 |
2022-10-24 | x86: consolidate VPCLMUL tests | Jan Beulich | 15 | -268/+156 |
2022-10-24 | x86: consolidate VAES tests | Jan Beulich | 15 | -352/+211 |
2022-10-24 | x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns | Jan Beulich | 31 | -361/+361 |
2022-10-21 | Support Intel AMX-FP16 | Cui,Lili | 9 | -1/+97 |
2022-10-20 | x86: Check VEX/EVEX encoding before checking vector operands | H.J. Lu | 5 | -4/+8 |
2022-10-20 | x86: re-work AVX-VNNI support | Jan Beulich | 7 | -12/+36 |
2022-10-19 | aarch64-pe support for LD, GAS and BFD | Jedidiah Thompson | 8 | -25/+108 |
2022-10-18 | x86: generalize gas documentation for disabling of ISA extensions | Jan Beulich | 1 | -49/+5 |
2022-10-17 | Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp} | CaiJingtao | 5 | -205/+566 |
2022-10-16 | PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many | Alan Modra | 5 | -56/+55 |
2022-10-14 | PowerPC SPE disassembly and tests | Alan Modra | 4 | -14/+11 |
2022-10-14 | e200 LSP support | Alan Modra | 5 | -12/+38 |
2022-10-14 | RISC-V: Imply 'Zicsr' from privileged extensions with CSRs | Tsukasa OI | 1 | -0/+6 |
2022-10-14 | RISC-V: Test DWARF register number for "fp" | Tsukasa OI | 2 | -0/+4 |
2022-10-12 | x86: drop "regmask" static variable | Jan Beulich | 1 | -3/+2 |
2022-10-11 | Re: Error: attempt to get value of unresolved symbol `L0' | Nick Clifton | 4 | -10/+26 |
2022-10-11 | add --enable-default-compressed-debug-sections-algorithm configure option | Martin Liska | 5 | -3/+40 |
2022-10-11 | refactor usage of compressed_debug_section_type | Martin Liska | 1 | -25/+9 |
2022-10-11 | Error: attempt to get value of unresolved symbol `L0' | Nick Clifton | 2 | -2/+12 |
2022-10-05 | x86/gas: support quoted address scale factor in AT&T syntax | Jan Beulich | 4 | -12/+35 |
2022-10-05 | Arm64: support CLEARBHB alias | Jan Beulich | 2 | -1/+3 |
2022-10-04 | gas: NEWS: Mention the T-Head extensions that were recently added | Palmer Dabbelt | 1 | -0/+5 |
2022-10-04 | Re: compress .gnu.debuglto_.debug_* sections if requested | Alan Modra | 1 | -13/+7 |
2022-10-04 | compress .gnu.debuglto_.debug_* sections if requested | Martin Liska | 1 | -1/+3 |
2022-10-04 | RISC-V/gas: allow generating up to 176-bit instructions with .insn | Jan Beulich | 7 | -10/+82 |
2022-10-04 | RISC-V/gas: don't open-code insn_length() | Jan Beulich | 1 | -1/+1 |