aboutsummaryrefslogtreecommitdiff
path: root/gas
AgeCommit message (Expand)AuthorFilesLines
2024-05-17aarch64: correct SVE2.1 ld2q (scalar plus scalar)Jan Beulich1-1/+1
2024-05-17aarch64: correct SVE2.1 ld{3,4}q / st{3,4}q (scalar plus immediate)Jan Beulich3-13/+13
2024-05-17LoongArch: gas: Adjust DWARF CIE alignment factorsmengqinggang1-5/+9
2024-05-16gas: sframe: fix typo to use FP instead of BPIndu Bhagat1-4/+4
2024-05-16aarch64: fp8 convert and scale - add sme2 insn variantsVictor Do Nascimento6-2/+623
2024-05-16aarch64: fp8 convert and scale - add sve2 insn variantsVictor Do Nascimento7-0/+313
2024-05-16aarch64: fp8 convert and scale - Add advsimd insn variantsVictor Do Nascimento5-0/+581
2024-05-16aarch64: fp8 convert and scale - add feature flags and related structuresVictor Do Nascimento2-0/+3
2024-05-16aarch64: add SPMU feature and its associated registersMatthieu Longo3-0/+27
2024-05-16Move assembler "IRP \+" test into a separate file. Add XFAILs for targets th...Nick Clifton6-9/+19
2024-05-16arm: remove incorrect handling of FP bignums in move_or_literal_poolRichard Earnshaw1-6/+24
2024-05-16Fix FAIL: macros altmacroAlan Modra1-5/+5
2024-05-15gas: Fix \+ expansion for .irp and .irpcFangrui Song3-1/+10
2024-05-15aarch64: Add sysreg features to +d128 dependenciesAndrew Carlotti1-2/+5
2024-05-15aarch64: Add simd dependency to +sha2Andrew Carlotti1-1/+1
2024-05-15aarch64: testsuite: share test utils macros and use themMatthieu Longo23-519/+576
2024-05-15aarch64: testsuite: reorder write and read to match macro orderMatthieu Longo11-292/+286
2024-05-15aarch64: testsuite: use same regs for read and write testsMatthieu Longo8-377/+377
2024-05-15aarch64: testsuite: replace instruction addresses by regexMatthieu Longo1-28/+28
2024-05-14Fix gas's 'macro count' test for various targetsNick Clifton2-10/+15
2024-05-14arm: update documentation for removal of the Maverick extensionRichard Earnshaw1-7/+4
2024-05-14arm: opcodes: remove Maverick disassembly.Richard Earnshaw2-8/+8
2024-05-14arm: remove Maverick support from the assembler.Richard Earnshaw1-179/+4
2024-05-14arm: remove tests for Maverick FPU extensionsRichard Earnshaw12-2010/+0
2024-05-13Add new assembler macro pseudo-variable \+ which counts the number of times a...Nick Clifton10-14/+77
2024-05-08RISC-V: Support B, Zaamo and Zalrsc extensions.Nelson Chu13-10/+25
2024-05-06x86: Drop using extension_opcode to encode vvvv registerCui, Lili3-6/+17
2024-05-06x86: Drop SwapSourcesCui, Lili1-8/+11
2024-05-06x86: Use vexvvvv as the switch state to encode the vvvv registerCui, Lili1-15/+17
2024-05-03x86/APX: further extend SSE2AVX coverageJan Beulich3-0/+974
2024-05-03x86/APX: extend SSE2AVX coverageJan Beulich7-3/+613
2024-04-25bpf: fix calculation when deciding to relax branchDavid Faust7-43/+95
2024-04-25LoongArch: gas: Simplify relocations in sections without code flagJinyang He3-3/+19
2024-04-23arm: Fix MVE vmla encodingClaudio Bantaloukas3-1355/+2041
2024-04-22x86/APX: Add invalid check for APX EVEX.X4.Cui, Lili3-1/+9
2024-04-20LoongArch: Add -mignore-start-align optionmengqinggang3-21/+51
2024-04-16x86: Fix a memory leak in md_assembleH.J. Lu1-5/+8
2024-04-16gas: Free unused memory in scfi_ops_cleanupH.J. Lu1-0/+3
2024-04-16Gas Doc: Update example of how .altmacro affects the interpretation of macro ...Nick Clifton1-8/+3
2024-04-12Update description of macro keyword argument assignment in assembler document...Nick Clifton1-1/+34
2024-04-12gas: Fix memory leaks in gen-sframe.cH.J. Lu1-0/+4
2024-04-11gas: Fix a CFI label name memory leak in scfi.cH.J. Lu2-2/+3
2024-04-11gas: Fix memory leaks in ginsn.cH.J. Lu1-3/+11
2024-04-10x86-64: Use long NOPs for Intel Core processorsH.J. Lu5-9/+397
2024-04-10gas: scfi: bugfixes for SCFI state propagationIndu Bhagat5-8/+87
2024-04-10gas: gcfg: add_bb_at_ginsn must return root_bbIndu Bhagat5-26/+164
2024-04-09arm: Fix disassembly of MVE vq[r]shr[u]nAlex Coplan3-1808/+1875
2024-04-09arm: Fix encoding of MVE vqshr[u]nAlex Coplan1-4/+4
2024-04-09RISC-V: Support Zcmp push/pop instructions.Jiawei8-0/+525
2024-04-09Support {evex} pseudo prefix for decode evex promoted insns without egpr32.Hu, Lin110-0/+1426