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2018-10-05x86: Add Intel ENCLV to assembler and disassemblerH.J. Lu5-0/+11
2018-10-05[Arm, 3/3] Add Execution and Data Prediction instructions for AArch32Sudakshina Das8-0/+63
2018-10-05[Arm, 2/3] Add instruction SB for AArch32Sudakshina Das10-0/+83
2018-10-05[Arm, 1/3] Add -march=armv8.5-a and related internal feature macros to AArch32Sudakshina Das4-0/+27
2018-10-05or1k: Add OpenRISC gas documentationStafford Horne6-0/+321
2018-10-05or1k: Add the l.muld, l.muldu, l.macu, l.msbu insnsRichard Henderson3-0/+52
2018-10-05or1k: Add the l.adrp insn and supporting relocationsStafford Horne8-0/+73
2018-10-05or1k: Add relocations for high-signed and low-storesRichard Henderson8-8/+159
2018-10-03AArch64: Add MOVPRFX tests and update testsuiteTamar Christina72-0/+949
2018-10-03AArch64: Constraint disassembler and assembler changes.Tamar Christina6-245/+261
2018-10-03AArch64: Close sequences at the end of sectionsTamar Christina3-0/+27
2018-10-03AArch64: Add SVE constraints verifier.Tamar Christina2-2/+8
2018-10-03AArch64: Wire through instr_sequenceTamar Christina3-8/+34
2018-10-02RISC-V: Add fence.tso instructionPalmer Dabbelt3-0/+18
2018-09-26Skip broken assembler test on Windows host.Sandra Loosemore2-1/+10
2018-09-25S/390: Fix symbolic displacement in layAndreas Krebbel4-1/+8
2018-09-21Correct ChangeLog entry for commit b8426d169d3f8aH.J. Lu1-1/+1
2018-09-21gas: Make bfin-parse.c/rl78-parse.c/rx-parse.c depend on bfd/reloc.cH.J. Lu3-6/+14
2018-09-21Fix more fallout from 17f6ade235fcAlan Modra2-3/+6
2018-09-20gas: Update expected outputs of "readelf -wL"H.J. Lu12-70/+86
2018-09-20S12Z/GAS: Correct a signed vs unsigned comparison error with GCC 4.1Maciej W. Rozycki2-11/+18
2018-09-20PPC/GAS: Correct a signed vs unsigned comparison error with GCC 4.1Maciej W. Rozycki2-1/+6
2018-09-20ARC: Fix build errors with large constants and C89Maciej W. Rozycki2-2/+7
2018-09-20Andes Technology has good news for you, we plan to update the nds32 port of b...Nick Clifton15-1643/+3027
2018-09-18Fix Aarch64 bug in warning filtering.Tamar Christina2-1/+6
2018-09-17RISC-V: bge[u] should get higher priority than ble[u].Jim Wilson3-0/+23
2018-09-17x86: Set EVex=2 on EVEX.128 only vmovd and vmovqH.J. Lu6-0/+79
2018-09-17x86: Set Vex=1 on VEX.128 only vmovd and vmovqH.J. Lu12-336/+131
2018-09-17x86: Add -mvexwig=[0|1] option to assemblerH.J. Lu13-11/+1545
2018-09-17Remove bogus notarget in gas teststuiteAlan Modra15-18/+20
2018-09-17A few hppa testcase tidiesAlan Modra4-16/+11
2018-09-17Ensure that binutils test names are unique.Nick Clifton8-7/+19
2018-09-15x86: Set Vex=1 on VEX.128 only vmovqH.J. Lu5-32/+40
2018-09-15Consolidate run_dump_testAlan Modra3-496/+8
2018-09-15run_dump_test replace PROG with DUMPPROG in gas and ldAlan Modra33-54/+90
2018-09-15gas testuite fixes: don't match dump.oAlan Modra246-253/+503
2018-09-15gas run_dump_test rename stderr and error-outputAlan Modra427-448/+877
2018-09-15gas run_dump_test rename not-target and not-skipAlan Modra151-169/+323
2018-09-15Remove run_dump_test support for objcopy as a dump programAlan Modra4-28/+24
2018-09-14x86: Check non-WIG EVEX instruction encoding with -mevexwig=1H.J. Lu6-0/+68
2018-09-14x86: Support VEX/EVEX WIG encodingH.J. Lu2-17/+21
2018-09-14x86: Handle unsupported static rounding in vcvt[u]si2sd in 32-bit modeH.J. Lu2-2/+7
2018-09-14x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32-bit modeH.J. Lu4-0/+35
2018-09-14csky: Support PC relative diff relocationLifang Xia3-0/+18
2018-09-14x86: fold CRC32 templatesJan Beulich2-11/+12
2018-09-13x86: Swap destination/source to encode VEX only if possibleH.J. Lu2-3/+9
2018-09-13x86: also allow D on 3-operand insnsJan Beulich2-19/+29
2018-09-13x86: use D attribute also for SIMD templatesJan Beulich6-9/+126
2018-09-13x86: fold ILP32 output of "opts" testsJan Beulich5-1296/+12
2018-09-13x86: improve operand reversalJan Beulich6-11/+970
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