rocket-tools/riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-08-30	MIPS/BFD: Correct microMIPS cross-mode BAL to JALX relaxation	Maciej W. Rozycki	6	-0/+114
2017-08-30	MIPS/GAS: Also respect `-mignore-branch-isa' with MIPS16 code	Maciej W. Rozycki	23	-1/+411
2017-07-26	S/390: Support z14 as CPU name.	Andreas Krebbel	3	-3/+3
2017-07-25	Bump version.	Tristan Gingold	2	-10/+14
2017-07-25	Version 2.28.1	Tristan Gingold	4	-9669/+9155
2017-07-24	[Patch, ARM] Relax the restrictions on REG_SP under Thumb mode on ARMv8-A	Jiong Wang	12	-18/+330
2017-07-05	[Patch ARM] Support MVFR2 VFP Coprocessor register for ARMv8-A	Ramana Radhakrishnan	6	-0/+36
2017-07-04	Fix ChangeLog entry	Thomas Preud'homme	1	-10/+0
2017-06-20	[ARM] Fix expansion of ldr pseudo instructionusers/ARM/embedded-binutils-2_28-branch-2017q2	Thomas Preud'homme	4	-24/+43
2017-06-20	Make import libraries relocatable objects	Thomas Preud'homme	1	-0/+10
2017-06-20	Fix building riscv targets with gcc v6.3.1	Nick Clifton	2	-1/+8
2017-04-04	RISC-V: Avoid a const warning	Palmer Dabbelt	2	-1/+6
2017-04-04	Allow ISA subsets to be disabled	Palmer Dabbelt	2	-0/+21
2017-03-30	Sanitize RISC-V GAS help text, documentation	Palmer Dabbelt	3	-7/+17
2017-03-30	RISC-V: Fix assembler for c.li, c.andi and c.addiw	Kito Cheng	2	-0/+14
2017-03-30	RISC-V: Define DWARF2_USE_FIXED_ADVANCE_PC.	Kuan-Lin Chen	2	-0/+7
2017-03-30	RISC-V: Fix DW_CFA_advance_loc relocation.	Kuan-Lin Chen	2	-0/+7
2017-03-30	RISC-V: Fix the offset of CFA relocation.	Kuan-Lin Chen	2	-10/+15
2017-03-27	PR21303, objdump doesn't show e200z4 insns	Alan Modra	4	-0/+25
2017-03-21	S/390: Remove vx2 facility flag	Andreas Krebbel	2	-4/+10
2017-03-09	Update -maltivec and -mvsx options to only enable their oldest instructions.	Peter Bergner	2	-2/+7
2017-03-08	Add support for the new 'lnia' extended mnemonic.	Peter Bergner	3	-2/+11
2017-03-02	Set version to 2.28, not a relase.	Tristan Gingold	2	-10/+14
2017-03-02	Add generated filesbinutils-2_28	Tristan Gingold	26	-10/+59019
2017-03-01	Nios2 dynobj handling fixes	Alan Modra	2	-0/+12
2017-02-28	PowerPC addpcis fix	Alan Modra	3	-81/+71
2017-02-27	sve	Richard Sandiford	7	-8/+5081
2017-02-27	sve	Richard Sandiford	5	-0/+62
2017-02-27	sve	Richard Sandiford	5	-0/+85
2017-02-27	sve	Richard Sandiford	2	-2/+6
2017-02-27	[AArch64] Add separate feature flag for weaker release consistent load insns	Richard Sandiford	5	-0/+33
2017-02-23	S/390: Add support for new cpu architecture - arch12.	Andreas Krebbel	7	-12/+411
2017-02-14	Fix powerpc testsuite source errors	Alan Modra	4	-22/+28
2017-02-11	POWER9 add scv/rfscv instruction support	Nicholas Piggin	3	-0/+10
2017-02-01	RISC-V gas: Remove em=linux from configure.tgt	Sebastian Huber	2	-1/+5
2017-01-30	MIPS: Add options to control branch ISA checks	Maciej W. Rozycki	11	-0/+267
2017-01-30	MIPS/GAS/testsuite: Convert branch local list tests to dump tests	Maciej W. Rozycki	8	-12/+35
2017-01-18	PR gas/20649: MIPS: Fix GOT16/LO16 reloc pairing with comdat sections	Maciej W. Rozycki	5	-5/+89
2017-01-18	Fix lex source files so that they will be accepted by flex v2.6.3	Bernhard Rosenkranzer	3	-17/+10
2017-01-16	RISC-V/GAS: Support more relocs against constant addresses	Andrew Waterman	2	-3/+8
2017-01-16	RISC-V/GAS: Improve handling of invalid relocs	Andrew Waterman	2	-1/+15
2017-01-16	Remove some custom sections from RISC-V's default linker scripts	Palmer Dabbelt	1	-0/+7
2017-01-16	RISC-V/GAS: Correct branch relaxation for weak symbols.	Andrew Waterman	2	-0/+35
2017-01-13	Enable Intel AVX512_VPOPCNTDQ instructions	Igor Tsimbalist	10	-1/+421
2017-01-02	Update year range in copyright notice of all files.	Alan Modra	556	-558/+562
2017-01-02	ChangeLog rotation	Alan Modra	2	-5974/+5988
2016-12-23	MIPS16: Add ASMACRO instruction support	Maciej W. Rozycki	6	-0/+79
2016-12-23	MIPS16: Simplify extended operand handling	Maciej W. Rozycki	2	-1/+6
2016-12-23	MIPS16/GAS: Clean up invalid unextended operand handling	Maciej W. Rozycki	9	-2/+245
2016-12-23	MIPS16: Reassign `0' and `4' operand codes	Maciej W. Rozycki	2	-5/+11