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AgeCommit message (Expand)AuthorFilesLines
2019-12-12i386: Also check R12-R15 registers when optimizing testq to testbH.J. Lu3-0/+12
2019-12-12i386: Add tests for -malign-branch-boundary and -malign-branchH.J. Lu54-0/+2562
2019-12-11[gas][arm] Add -mwarn-restrict-itAndre Vieira8-8/+8
2019-12-11x86: further refine SSE check (SSE4a, SHA, GFNI)Jan Beulich5-25/+75
2019-12-10[gas][arm] Set context table for '.arch_extension'Andre Vieira2-0/+13
2019-12-09x86/Intel: support "mmword ptr"Jan Beulich5-3/+8
2019-12-09x86/Intel: fix "near ptr" / "far ptr" handlingJan Beulich2-0/+10
2019-12-08aarch64*-*-*ilp32 gas testsAlan Modra13-36/+34
2019-12-06[gas] Implement .cfi_negate_ra_state directiveKyrylo Tkachov2-0/+46
2019-12-05Arm64: correct "sha3" arch-extension directive handlingJan Beulich5-42/+35
2019-12-04x86-64: accept 64-bit LFS/LGS/LSS forms with suffix or operand size specifierJan Beulich7-8/+67
2019-12-04x86-64/Intel: fix CALL/JMP with dword operandJan Beulich2-4/+20
2019-12-04x86/Intel: extend MOVDIRI testingJan Beulich6-0/+12
2019-12-04x86: make sure all PUSH/POP honor DefaultSizeJan Beulich2-0/+16
2019-12-04x86: drop some stray/bogus DefaultSizeJan Beulich2-8/+84
2019-11-28gas/riscv: Produce version 3 DWARF CIE by defaultAndrew Burgess2-0/+17
2019-11-28gas: Check for overflow on return column in version 1 CIE DWARFAndrew Burgess3-0/+23
2019-11-28binutils/gas/riscv: Add DWARF register numbers for CSRsAndrew Burgess2-0/+520
2019-11-25Fix "psb CSYNC" and "bti C".Andrew Pinski5-0/+12
2019-11-22Arm: Change CRC from fpu feature to archititectural extensionMihail Ionescu2-0/+33
2019-11-20PR24944, gas doesn't read enough digits when parsing a floating point numberAlan Modra2-3/+10
2019-11-18gas: Add --gdwarf-cie-version command line flagAndrew Burgess7-0/+71
2019-11-14x86/Intel: correct CMPSD test cases' regexp closing paren placementJan Beulich2-39/+39
2019-11-14x86/Intel: extend MOVSD/CMPSD testsuite coverageJan Beulich9-0/+374
2019-11-12RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive.Jim Wilson1-1/+1
2019-11-12[gas][arm] Enable VLDM, VSTM, VPUSH, VPOP for MVEMihail Ionescu2-0/+51
2019-11-12[binutils][arm] Update the decoding of MVE VMOV, VMVNMihail Ionescu2-0/+88
2019-11-12[gas][arm] Make .fpu reset the FPU/Coprocessor feature bitsMihail Ionescu3-0/+23
2019-11-12x86: eliminate ImmExt abuseJan Beulich10-304/+325
2019-11-11Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same registerJan Beulich2-0/+4
2019-11-08i386: Only check suffix in instruction mnemonicH.J. Lu4-2/+27
2019-11-07[gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X]Matthew Malcomson2-0/+15
2019-11-07[Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]Matthew Malcomson3-1/+69
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson8-0/+304
2019-11-07[Patch][binutils][aarch64] .bfloat16 directive for AArch64 [7/10]Matthew Malcomson3-0/+41
2019-11-07[Patch][binutils][arm] .bfloat16 directive for Arm [6/X]Matthew Malcomson3-0/+41
2019-11-07[binutils][arm] BFloat16 enablement [4/X]Matthew Malcomson15-0/+544
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson7-0/+350
2019-11-07x86: support further AMD Zen2 instructionsJan Beulich7-54/+22
2019-11-07x86: adjust register names printed for MONITOR/MWAITJan Beulich11-201/+61
2019-10-31i386; Add .code16gcc fldenv testsH.J. Lu2-2/+15
2019-10-31Add support for context sensitive '.arch_extension' to the ARM assembler.Mihail Ionescu4-0/+25
2019-10-30Modify the ARNM assembler to accept the omission of the immediate argument fo...Delia Burduv4-29/+45
2019-10-30x86: add tests to cover defaulting of operand sizes for ambiguous insnsJan Beulich7-0/+385
2019-10-09Fix the disassembly of the LDS and STS instructions of the AVR architecture.Nick Clifton2-0/+13
2019-10-07Add support for new functionality in the msp430 backend of GCC.Jozef Lawrynowicz13-0/+57
2019-10-07x86/Intel: correct MOVSD and CMPSD handlingJan Beulich8-10/+231
2019-09-24Arm: Fix out of range conditional branch (PR/24991)Tamar Christina3-0/+11
2019-09-24[ARM]: Modify assembler to accept floating and signless datatypes for MVE ins...Srinath Parvathaneni4-1/+76
2019-09-20x86-64: fix handling of PUSH/POP of segment registerJan Beulich2-2/+14
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