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AgeCommit message (Expand)AuthorFilesLines
2018-07-16x86: fix operand size checkingJan Beulich2-32/+46
2018-07-13Add a test that relocs are correctly generated for missing build notes.Nick Clifton3-0/+22
2018-07-13Allow bit-patterns in the immediate field of ARM neon mov instructions.Nick Clifton2-0/+7
2018-07-12This patch adds support for the SSBB and PSSBB speculation barrier instructio...Nick Clifton2-363/+367
2018-07-12Add remainder of Em16 restrictions for AArch64 gas.Tamar Christina3-0/+198
2018-07-11Adds the speculation barrier instructions to the ARM assembler and disassembler.Sudakshina Das6-6/+17
2018-07-11x86/Intel: accept memory operand size specifiers for CET insnsJan Beulich6-0/+18
2018-07-11x86: fix "REP RET" with -madd-bnd-prefixJan Beulich6-4/+22
2018-07-09 * testsuite/nds32/ji-jr.d: Fix name tag.Jeff Law1-1/+1
2018-07-06Fix the read/write flag for these registers on AArch64Tamar Christina2-0/+26
2018-07-02microMIPS/GAS: Handle several percent-ops with macrosMaciej W. Rozycki6-0/+652
2018-07-02microMIPS/BFD: Add missing NewABI TLS and miscellaneous relocationsMaciej W. Rozycki3-0/+278
2018-06-29[Patch AArch64] Warn on unpredictable stlxrb , stlxrh and stlxr cases.Ramana Radhakrishnan2-0/+21
2018-06-29Fix AArch64 encodings for by element instructions.Tamar Christina5-40638/+64832
2018-06-26Fix the MSP430 assembler's parsing of register names.Nick Clifton1-125/+125
2018-06-22Correct negs aliasing on AArch64.Tamar Christina2-0/+175
2018-06-20Change the ARM assembler's ADR and ADRl pseudo-ops so that they will only set...Nick Clifton3-1/+4
2018-06-20RISC-V: Accept constant operands in la and llaSebastian Huber7-0/+79
2018-06-14MIPS: Add Global INValidate ASE supportFaraz Shahbazker10-0/+66
2018-06-13MIPS: Add CRC ASE supportScott Egerton15-0/+167
2018-06-08Prevent undefined FMOV instructions being accepted by the AArch64 assembler.Egeyar Bagcioglu4-1/+90
2018-06-01x86: don't emit REX.W for SLDT and STRJan Beulich2-4/+4
2018-06-01x86: relax redundant REX prefix checkJan Beulich3-0/+26
2018-06-01x86/Intel: accept "oword ptr" for INVPCIDJan Beulich6-0/+6
2018-05-30Add znver2 support.Amit Pawar9-34/+135
2018-05-24RISC-V: Fix .align handling when .option norelax.Jim Wilson4-0/+41
2018-05-21Remove fake operand handling for extended mnemonics.Peter Bergner4-441/+459
2018-05-18Add support for the Freescale s12z processor.John Darrington201-0/+3602
2018-05-15Implement Read/Write constraints on system registers on AArch64Tamar Christina6-5/+25
2018-05-10Allow integer immediates for AArch64 fmov instructions.Tamar Christina6-22/+23
2018-05-10Allow integer immediate for VFP vmov instructions.Tamar Christina2-0/+19
2018-05-09gas: xtensa: fix literal movementMax Filippov7-0/+68
2018-05-09Fix binary compatibility between GCC and the TI compiler for the PRU target.Dimitar Dimitrov4-4/+12
2018-05-08RISC-V: Add missing hint instructions from RV128I.Jim Wilson4-2/+18
2018-05-07Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu11-0/+136
2018-05-06gas/i386/xmmhi32.d: Also allow dir32 relocationH.J. Lu1-42/+42
2018-05-06i386: Append ".p2align 4,0" to gas testsH.J. Lu8-0/+12
2018-04-27testsuite: Support filtering targets by TCL procedure in `run_dump_test'Maciej W. Rozycki1-16/+20
2018-04-27Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist11-136/+0
2018-04-26Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist11-0/+136
2018-04-26x86: also optimize zeroing-masking variants of insnsJan Beulich6-72/+72
2018-04-26x86: properly force / avoid forcing EVEX encodingJan Beulich5-0/+60
2018-04-26x86: CpuXSAVE is a prereq for various other featuresJan Beulich3-0/+49
2018-04-26x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMaskJan Beulich5-0/+89
2018-04-26x86: don't recognize bnd<N> as registers without CpuMPXJan Beulich3-0/+19
2018-04-26x86: x87-related adjustmentsJan Beulich5-0/+42
2018-04-25[ARM] Add FDPIC relocations definitionsChristophe Lyon2-0/+29
2018-04-25Fix the mask for the sqrdml(a|s)h instructions.Tamar Christina3-125/+10058
2018-04-25Remove arm-aout and arm-coff supportAlan Modra151-152/+148
2018-04-20RISC-V: Add new option -mrelax/-mno-relax.Jim Wilson4-0/+45
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