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AgeCommit message (Expand)AuthorFilesLines
2023-04-25RISC-V: test for expected / no unexpected symbolsJan Beulich3-0/+22
2023-04-25RISC-V: avoid redundant and misleading/wrong error messagesJan Beulich1-1/+0
2023-04-23LoongArch: Fix loongarch32 test failsmengqinggang1-7/+7
2023-04-20x86: adjust an ILP32 testcase using .insnJan Beulich1-1/+1
2023-04-18Symbols with GOT relocatios do not fix adjustbalemengqinggang2-69/+69
2023-04-13arc: Update ARC's CFI tests.Claudiu Zissulescu2-11/+11
2023-04-13arc: Update GAS testClaudiu Zissulescu2-8/+0
2023-04-12Fail of x86_64 AMX-COMPLEX insns (Intel disassembly)Alan Modra1-0/+1
2023-04-10x86: Add inval tests for AMX instructionsHaochen Jiang7-8/+60
2023-04-07Support Intel AMX-COMPLEXHaochen Jiang8-0/+98
2023-04-03opcodes/arm: adjust whitespace in cpsie instructionAndrew Burgess2-4/+4
2023-03-31x86: convert testcases to use .insnJan Beulich39-523/+346
2023-03-31x86: handle immediate operands for .insnJan Beulich4-1/+74
2023-03-31x86: handle EVEX Disp8 for .insnJan Beulich4-0/+52
2023-03-31x86: process instruction operands for .insnJan Beulich4-0/+130
2023-03-31x86: parse VEX and alike specifiers for .insnJan Beulich4-0/+12
2023-03-31x86: introduce .insn directiveJan Beulich5-0/+58
2023-03-30aarch64: Add the RPRFM instructionRichard Sandiford6-1/+181
2023-03-30aarch64: Add the SVE FCLAMP instructionRichard Sandiford8-1/+102
2023-03-30aarch64: Add new SVE shift instructionsRichard Sandiford7-0/+97
2023-03-30aarch64: Add new SVE saturating conversion instructionsRichard Sandiford7-0/+93
2023-03-30aarch64: Add new SVE dot-product instructionsRichard Sandiford8-12/+185
2023-03-30aarch64: Add the SVE BFMLSL instructionsRichard Sandiford7-0/+143
2023-03-30aarch64: Add the SME2 UZP and ZIP instructionsRichard Sandiford7-0/+352
2023-03-30aarch64: Add the SME2 UNPK instructionsRichard Sandiford7-0/+188
2023-03-30aarch64: Add the SME2 shift instructionsRichard Sandiford14-0/+370
2023-03-30aarch64: Add the SME2 saturating conversion instructionsRichard Sandiford14-0/+328
2023-03-30aarch64: Add the SME2 FP<->FP conversion instructionsRichard Sandiford7-0/+102
2023-03-30aarch64: Add the SME2 FP<->int conversion instructionsRichard Sandiford7-0/+245
2023-03-30aarch64: Add the SME2 CLAMP instructionsRichard Sandiford7-0/+407
2023-03-30aarch64: Add the SME2 MOPA and MOPS instructionsRichard Sandiford7-0/+177
2023-03-30aarch64: Add the SME2 vertical dot-product instructionsRichard Sandiford28-0/+556
2023-03-30aarch64: Add the SME2 dot-product instructionsRichard Sandiford28-0/+2355
2023-03-30aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford21-0/+2312
2023-03-30aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford7-0/+2080
2023-03-30aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford14-0/+1127
2023-03-30aarch64: Add the SME2 maximum/minimum instructionsRichard Sandiford8-6/+2218
2023-03-30aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford21-0/+1422
2023-03-30aarch64: Add the SME2 ZT0 instructionsRichard Sandiford10-3/+682
2023-03-30aarch64: Add the SME2 predicate-related instructionsRichard Sandiford25-10/+2609
2023-03-30aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford28-0/+6793
2023-03-30aarch64: Add the SME2 MOVA instructionsRichard Sandiford9-2/+1590
2023-03-30aarch64: Add support for predicate-as-counter registersRichard Sandiford14-0/+299
2023-03-30aarch64; Add support for vector offset rangesRichard Sandiford10-0/+61
2023-03-30aarch64: Add support for vgx2 and vgx4Richard Sandiford12-0/+87
2023-03-30aarch64: Prefer register ranges & support wrappingRichard Sandiford10-977/+1031
2023-03-30aarch64: Add support for strided register listsRichard Sandiford3-7/+15
2023-03-30aarch64: Tweak priorities of parsing-related errorsRichard Sandiford1-6/+6
2023-03-30aarch64: Try to report invalid variants against the closest matchRichard Sandiford3-93/+97
2023-03-30aarch64: Tweak register list errorsRichard Sandiford3-16/+16
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