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2015-07-24Fix the evaluation of RL78 complex relocs, by making immediate values be comp...Nick Clifton5-1/+21
2015-07-24Remove leading/trailing white spaces in ChangeLogH.J. Lu1-1/+1
2015-07-22Fix memory operand size for vcvtt?ps2u?qq instructionsH.J. Lu13-240/+331
2015-07-21[ARM] Support correctly spelled ARMv6KZ architecture namesMatthew Wahab3-0/+33
2015-07-16Updates the ARM disassembler's output of floating point constants to include ...Alessandro Marzocchi1-2/+2
2015-07-16[AArch64][2/3] GAS support BFD_RELOC_AARCH64_TLSLD_ADR_PREL21Jiong Wang5-0/+40
2015-07-16[ARM] Make human parsing of "processor does not support instruction in mode" ...James Greenhalgh7-137/+146
2015-07-10Updated to accept .debug_* sectionsH.J. Lu2-2/+6
2015-07-10Add missing changelog entriesAlan Modra1-0/+6
2015-07-08Define DIFF_EXPR_OK for avr target to allow PC relative difference relocation.Denis Chertykov3-0/+59
2015-07-03Remove ppc860, ppc750cl, ppc7450 insns from common ppc.Alan Modra2-2/+6
2015-07-01Assembler tests for Nios II R2Sandra Loosemore123-0/+3862
2015-06-30Add support for monitorx/mwaitx instructionsAmit Pawar16-4/+304
2015-06-27Update ia64 gas testsH.J. Lu3-2/+7
2015-06-25Update .strtab section sizes in mmix testsH.J. Lu3-2/+7
2015-06-25Use strtab with GC and suffix merging for .strtabH.J. Lu4-0/+24
2015-06-22PPC sync instruction accepts invalid and incompatible operandsPeter Bergner3-4/+9
2015-06-22Stop "objdump -d" from disassembling past a symbolic address.Nick Clifton7-36/+48
2015-06-19Allow for optional operands with non-zero default values.Peter Bergner4-5/+11
2015-06-18Add support for using the ADR alias in Thumb mode against nearby symbols.Nick Clifton4-0/+27
2015-06-18Fix the computation of the addends for an ARM_TLS_LE32 reloc.Nick Clifton3-0/+48
2015-06-17Add support for converting LDR Rx,=<imm> to MOV or MVN in Thumb2 mode.Alessandro Marzocchi5-0/+66
2015-06-17Add support for converting VLDR <reg>,=<constant> to a VMOV instruction when ...Alessandro Marzocchi7-0/+278
2015-06-16[AArch64] Support id_mmfr4 system registerMatthew Wahab3-11/+18
2015-06-15[AArch64] Gas add BFD_RELOC_AARCH64_LD64_GOTOFF_LO15 supportRenlin Li3-15/+24
2015-06-15gas: Don't use frag_align but use plain padding to align .debug_aranges.Mark Wielaard3-0/+38
2015-06-04Add hwsync extended mnemonic.Peter Bergner3-4/+18
2015-06-03[ARM] Commit approaved testcases missed in previous commitMatthew Wahab3-0/+142
2015-06-02[ARM] Add support for ARMv8.1 PAN extensionMatthew Wahab3-9/+39
2015-06-02[AArch64] Support for ARMv8.1a Adv.SIMD instructionsMatthew Wahab4-0/+223
2015-06-02[AArch64] Support for ARMv8.1a Limited Ordering Regions extensionMatthew Wahab4-0/+97
2015-06-01[AArch64][GAS] Add support for PAN architecture extensionMatthew Wahab4-0/+65
2015-06-01[AArch64] GAS support BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14Jiong Wang3-0/+8
2015-06-01[AArch64] GAS Support BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15Jiong Wang3-15/+25
2015-06-01x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand orderJan Beulich7-432/+439
2015-06-01x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}Jan Beulich3-72/+81
2015-05-28Compact EH SupportCatherine Moore27-1/+783
2015-05-15Support AMD64/Intel ISAs in assembler/disassemblerH.J. Lu8-2/+61
2015-05-15Add -mshared option to x86 ELF assemblerH.J. Lu8-25/+163
2015-05-14Fix some PPC assembler errors.Peter Bergner7-9/+30
2015-05-13xtensa: fix gas trampolines regressionMax Filippov2-0/+14
2015-05-13Revert "Add -mno-shared to x86 assembler"H.J. Lu4-73/+0
2015-05-13Add missing ChangeLog entries for PR binutis/18386H.J. Lu1-0/+11
2015-05-11Add Intel MCU support to gasH.J. Lu14-2/+200
2015-05-09Ignore 0x66 prefix for call/jmp/jcc in 64-bit modeH.J. Lu6-6/+105
2015-05-08Change ARM symbol name verification code so that it only triggers when the fo...Nick Clifton3-1/+19
2015-05-08Add -mno-shared to x86 assemblerH.J. Lu4-0/+73
2015-05-07Optimize branches to non-weak symbols with visibilityH.J. Lu5-0/+112
2015-05-06gas: added tests for the sparc natural instructions.Jose E. Marchesi5-5/+53
2015-05-06gas: support for the sparc %ncc condition codes register.Jose E. Marchesi6-0/+42
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