rocket-tools/riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-11-28	gas: change meaning of ; in the BPF assembler	Jose E. Marchesi	9	-30/+30
2023-11-28	testsuite: Clean up .allow_index_reg in i386 tests	Haochen Jiang	234	-574/+350
2023-11-28	testsuite: Clean up #as in dump file for i386 tests	Haochen Jiang	262	-262/+0
2023-11-27	as: Add new estimated reciprocal instructions in LoongArch v1.1	Jiajie Chen	4	-0/+24
2023-11-27	as: Add new atomic instructions in LoongArch v1.1	Jiajie Chen	2	-0/+84
2023-11-24	x86: also prefer VEX encoding over EVEX one for VCVTNEPS2BF16 when possible	Jan Beulich	2	-7/+48
2023-11-23	s390: Add missing extended mnemonics	Jens Remus	12	-3/+60
2023-11-23	s390: Align optional operand definition to specs	Jens Remus	6	-10/+27
2023-11-23	s390: Add brasl edge test cases from ESA to z/Architecture	Jens Remus	2	-0/+12
2023-11-23	s390: Position independent verification of relative addressing	Jens Remus	6	-237/+237
2023-11-23	MIPS/GAS: Use addiu instead of addi in test elf-rel.	YunQiang Su	3	-30/+30
2023-11-23	MIPS/GAS: Fix test failures due to jr encoding changes on r6	YunQiang Su	5	-5/+5
2023-11-23	RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extension	Jin Ma	2	-0/+68
2023-11-23	RISC-V: Add vector mask instructions for T-Head VECTOR vendor extension	Jin Ma	2	-0/+56
2023-11-23	RISC-V: Add reductions instructions for T-Head VECTOR vendor extension	Jin Ma	2	-0/+68
2023-11-23	RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor e...	Jin Ma	2	-0/+358
2023-11-23	RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor exte...	Jin Ma	2	-0/+178
2023-11-23	RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extension	Jin Ma	2	-0/+657
2023-11-23	RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extension	Jin Ma	2	-0/+155
2023-11-23	RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extension	Jin Ma	2	-0/+1708
2023-11-23	RISC-V: Add load/store instructions for T-Head VECTOR vendor extension	Jin Ma	2	-0/+268
2023-11-23	RISC-V: Add configuration-setting instructions for T-Head VECTOR vendor exten...	Jin Ma	2	-0/+15
2023-11-23	RISC-V: Add CSRs for T-Head VECTOR vendor extension	Jin Ma	4	-0/+53
2023-11-23	RISC-V: Add T-Head VECTOR vendor extension.	Jin Ma	3	-0/+5
2023-11-22	LoongArch: fix internal error when as handling unsupported modifier.	Lulu Cai	3	-0/+8
2023-11-21	bpf: Fixed register parsing disambiguating with possible symbol.	Cupertino Miranda	1	-0/+3
2023-11-18	gas: bpf: do not allow referring to register names as symbols in operands	Jose E. Marchesi	4	-0/+19
2023-11-17	bpf: avoid creating wrong symbols while parsing	David Faust	3	-0/+11
2023-11-17	x86: improve a few diagnostics	Jan Beulich	8	-75/+75
2023-11-17	x86: CPU-qualify {disp16} / {disp32}	Jan Beulich	4	-18/+58
2023-11-17	x86-64: extend expected-size check in check_qword_reg()	Jan Beulich	2	-18/+24
2023-11-16	aarch64: Add support for VMSA feature enhancements.	Srinath Parvathaneni	3	-0/+166
2023-11-16	aarch64: Add new AT system instructions.	Srinath Parvathaneni	3	-0/+11
2023-11-16	aarch64: Add support to new features in RAS extension.	Srinath Parvathaneni	5	-4/+81
2023-11-16	aarch64: Add features to the Statistical Profiling Extension.	Srinath Parvathaneni	4	-0/+18
2023-11-16	aarch64: Add SLC target for PRFM instruction.	Srinath Parvathaneni	2	-26/+32
2023-11-15	GAS/MIPS: add "--defsym r6=" for default when it's r6	YunQiang Su	1	-0/+5
2023-11-15	MIPS: Fix Irix gas testcases about pdr section	YunQiang Su	9	-7/+25
2023-11-10	GAS/MIPS: Fix testcase module-defer-warn2 for r2+ triples	YunQiang Su	4	-1/+14
2023-11-10	GAS/MIPS: Add mips16-e-irix.d testcase	YunQiang Su	2	-1/+51
2023-11-09	aarch64: Fix error in THE system register checking	Victor Do Nascimento	2	-0/+10
2023-11-07	aarch64: Add LSE128 instructions	Victor Do Nascimento	2	-0/+65
2023-11-07	aarch64: Add THE system register support	Victor Do Nascimento	2	-0/+9
2023-11-07	RISC-V: Add support for XCValu extension in CV32E40P	Mary Bennett	29	-0/+652
2023-11-07	RISC-V: Add support for XCVmac extension in CV32E40P	Mary Bennett	8	-0/+524
2023-11-06	RISC-V: Make sure rv32q conflict won't affect the fp-q-insns-32 gas testcase.	Nelson Chu	1	-1/+1
2023-11-03	gas: correct ignoring of C-style number suffixes	Jan Beulich	3	-0/+89
2023-11-03	RISC-V: Lx/Sx macro insn tests	Jan Beulich	2	-0/+70
2023-11-03	RISC-V: add F- and D-extension testcases	Jan Beulich	10	-0/+1111
2023-11-03	RISC-V: make FLQ/FSQ macro-insns work	Jan Beulich	4	-0/+506