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19 hoursAdd macros to get opcode of instructions approriatelyXin Wang1-18/+18
LoongArch: Add macros to get opcode and register of instructions appropriately Currently, we get opcode of an instruction by manipulate the binary with it's mask, it's a bit of a pain. Now a macro is defined to do this and a macro to get the RD and RJ registers which is applicable to most instructions of LoongArch are added.
38 hoursx86/APX: use D for 2-operand CFCMOVccJan Beulich1-1/+7
There's no need to have 30 redundant templates when we can easily take care of the operand swapping like we do for various other insns.
38 hoursx86/APX: optimize certain reg-only CFCMOVcc formsJan Beulich1-0/+35
Along the lines of 2513312930b2 ("x86/APX: apply NDD-to-legacy transformation to further CMOVcc forms") these can similarly be converted to the shorter legacy-encoded CMOVcc.
5 daysRISC-V: Add support for XCVsimd extension in CV32E40PMary Bennett1-0/+40
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvsimd` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * NEWS: Updated. * config/tc-riscv.c (validate_riscv_insn): Add custom operands. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVsimd as an additional ISA extension for CORE-V. * testsuite/gas/riscv/march-help.l: Add xcvsimd. * testsuite/gas/riscv/x-cv-simd.d: New test. * testsuite/gas/riscv/x-cv-simd.s: New test. * testsuite/gas/riscv/x-cv-simd-fail.d: New test. * testsuite/gas/riscv/x-cv-simd-fail.l: New test. * testsuite/gas/riscv/x-cv-simd-fail.s: New test. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVsimd. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVsimd. (enum riscv_insn_class): Add the XCVsimd instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add custom operands. * riscv-opc.c: Add XCVsimd instructions.
6 daysSupport ymm rounding control for Intel AVX10.2Haochen Jiang1-56/+64
In the patch, in order to support ymm rounding for AVX10.2, we derive evex attribute for all cases instead of only for rc_none to encode U bit. Also changed some bad_opcode return due to the share of U bit with APX_F. gas/ChangeLog: * config/tc-i386.c (cpu_flags_match): Handle AVX10_2. (build_evex_prefix): Handle U bit. Derive evex attribute for all cases. (check_VecOperands): Handle AVX10.2 and ymm roundings. * doc/c-i386.texi: Document .avx10.2. * testsuite/gas/i386/i386.exp: Run AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-rounding-intel.d: New test. * testsuite/gas/i386/avx10_2-rounding-inval.l: Ditto. * testsuite/gas/i386/avx10_2-rounding-inval.s: Ditto. * testsuite/gas/i386/avx10_2-rounding.d: Ditto. * testsuite/gas/i386/avx10_2-rounding.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding.s: Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add U bit. (get_valid_dis386): Handle U bit. * i386-gen.c (isa_dependencies): Add AVX10.2. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX10_2): New. (i386_cpu_flags): Add cpuavx10_2. * i386-opc.tbl: Add rounding to old entries which do not permit rounding previously. Also eliminate the redundant RegXMM for vcvtps2uqq. * i386-tbl.h: Regenerated.
8 daysx86: replace conditional operators used to calculate booleansJan Beulich1-10/+11
The boolean expressions themselves are fine to use there.
8 daysx86: limit RegRex64 useJan Beulich1-9/+7
The special property really only applies to the "extended" byte regs having legacy word/dword counterparts. While touching involved code also drop redundant byte checks from a conditional in establish_rex(): The other remaining RegRex64 uses only exist on registers which can't be used as register operands anyway. Hence RegRex64 as an attribute of a (valid) register operand implies that it's a byte reg.
9 daysLoongArch: LoongArch64 allows relocations to use 64-bit addendsLulu Cai1-0/+3
Relocations using 64-bit addends allow larger constant offset address calculations to be fused.
10 daysx86: Report invalid TLS operatorH.J. Lu1-2/+2
Report invalid TLS operator, instead of relocation. PR gas/28595 * config/tc-i386.c (gotrel): Replace int with unsigned int. (i386_assemble): Report invalid TLS operator. * testsuite/gas/i386/inval-tls.l: updated. * testsuite/gas/i386/x86-64-inval-tls.l: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
11 daysx86: Report invalid TLS relocation nameH.J. Lu1-91/+98
Get TLS relocation name from its lex_got entry when reporting invalid instructions with TLS relocations. PR gas/28595 * config/tc-i386.c (gotrel): Moved from ... (lex_got): There. (i386_assemble): Get invalid TLS relocation name from its lex_got entry when reporting TLS relocation error. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
11 daysx86: Allow R_386_TLS_LE_32 with KMOVDH.J. Lu1-2/+2
Since there is no TLS IE transition, allow R_386_TLS_LE_32 with KMOVD. gas/ PR gas/28595 * config/tc-i386.c (i386_assemble): Remove BFD_RELOC_386_TLS_LE_32 from TLS code check. * testsuite/gas/i386/inval-tls.s: Remove foo@tpoff(%eax). * testsuite/gas/i386/inval-tls.l: Updated. ld/ PR gas/28595 * testsuite/ld-i386/i386.exp: Run tlsle1. * testsuite/ld-i386/tlsle1.d: New file. * testsuite/ld-i386/tlsle1.s: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
12 daysRISC-V: PR32036, Support Zcmp cm.mva01s and cm.mvsa01 instructions.Jiawei1-0/+15
This patch supports Zcmp instruction 'cm.mva01s' and 'cm.mvsa01'. All disassemble instructions use the sreg format. Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> gas/ChangeLog: PR 32036 * NEWS: Updated. * config/tc-riscv.c (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/zcmp-mv.d: New test. * testsuite/gas/riscv/zcmp-mv.s: New test. include/ChangeLog: PR 32036 * opcode/riscv-opc.h (MATCH_CM_MVA01S): New opcode. (MASK_CM_MVA01S): New mask. (MATCH_CM_MVSA01): New opcode. (MASK_CM_MVSA01): New mask. (DECLARE_INSN): New declarations. * opcode/riscv.h (OP_MASK_SREG1): New mask. (OP_SH_SREG1): New operand code. (OP_MASK_SREG2): New mask. (OP_SH_SREG2): New operand code. (X_A0): New reg number. (X_A1): Ditto. (X_S7): Ditto. (RISCV_SREG_0_7): New macro function. opcodes/ChangeLog: PR 32036 * riscv-dis.c (riscv_zcmp_get_sregno): New function. (print_insn_args): New operators. * riscv-opc.c (match_sreg1_not_eq_sreg2): New match function.
2024-08-23x86: simplify SAE checkingJan Beulich1-12/+10
To determine whether SAE (with or without StaticRounding) is permitted there's no need to iterate over all operands. Even less so starting at the front (thus needlessly inspecting immediate operands as well). Leverage the pattern across all relevant templates and check only the last two operands, and also only for non-512 ones (besides the non-LIG case that was already checked for).
2024-08-23RISC-V: process rs_align_code also when relaxingJan Beulich1-32/+29
riscv_handle_align() runs after all input was processed. Whether relaxation is enabled for any particular piece of code is not recorded anywhere. (This issue was even "worked around" in a gas testcase, which is adjusted accordingly.) Furthermore, as demonstrated by an ld testcase, tail padding in an object file's executable sections depended on whether relaxation was enabled at the end of assembly: NOPs were emitted only when relaxation was off; zeroes were emitted with relaxation enabled. (It could probably be either way, but it should be independent of relaxation state at the end of assembly. Except of course write.c, in a comment ahead of #define-ing SUB_SEGMENT_ALIGN(), explicitly says "proper nop-filling".) While re-indenting, drop the "odd_padding" variable. It's used exactly once, and having the actual expression right in the if() is imo helping readers to understand what the intentions are. While touching the ld testcase, also tighten the expectations for the addresses of the two symbols: The last two digits have to have fixed values.
2024-08-19gas: ginsn: x86: pacify Wmaybe-uininitialized compiler warningIndu Bhagat1-0/+2
Fix PR binutils/32091 After commit d56083b5047b8e7cc9eda2f867bd2b75724920a1, some gcc versions may warn about unintialized usage of ginsn_func. Albeit false positive, adapt the code to escape the warning. gas/config/ * tc-i386-ginsn.c (x86_ginsn_indirect_branch): Early exit if unexpected args.
2024-08-16gas: don't open-code LEX_*NAMEJan Beulich5-6/+6
... except in read.c's definition of lex_type[], where readbility would otherwise suffer.
2024-08-15gas: pru: Fix trailing whitespace handlingDimitar Dimitrov1-0/+8
With commit 6ae8a30d44f016cafb46a75843b5109316eb1996, arguments followed by a C-style comment ended up with a trailing space. That extra space character confused the PRU register name matching, leading to spurious errors about unrecognized registers. This affected existing code like newlib's setjmp.s for pru. Fix by stripping the trailing whitespace for any argument. Even with 6ae8a30d44f016cafb46a75843b5109316eb1996 reverted, this patch is safe to be applied. Successfully regression-tested with GCC and newlib testsuites for pru-unknown-elf. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2024-08-14x86: correct .insn with opcode extension and VEX/XOP/EVEX encodingJan Beulich1-1/+2
When VexVVVV handling was re-worked, .insn broke: When an opcode extension is in use, VexVVVV_DST needs using now, as ModR/M.reg is already occupied, matching what c8866e3ec5e2 ("x86: Drop using extension_opcode to encode vvvv register") did. While adding (bad) POP2 forms, also slightly adjust existing ones: No need to use XMM registers, and no need to specify %r8 when really %rax is meant twice (EVEX.vvvv not really being the culprit there, or else EVEX.V' would also have needed mentioning).
2024-08-12Revert "gas: have scrubber retain more whitespace"H.J. Lu7-84/+28
This reverts commit 6ae8a30d44f016cafb46a75843b5109316eb1996. This fixes PR gas/32073.
2024-08-12Revert "gas: drop scrubber states 14 and 15"H.J. Lu2-0/+5
This reverts commit 7dd0dfbde7ee31167a3b2e192a575493d26b7b0a. This is a prerequisite for the PR gas/32073 fix.
2024-08-09gas: drop scrubber states 14 and 15Jan Beulich2-5/+0
While sadly 5262831592fb doesn't say anything on why these would have been needed, the latest with the removal of most of the opcode vs operands distinction in the scrubber these shouldn't be needed anymore. The implementation was a little questionable anyway, in moving back to states expecting labels, when clearly labels shouldn't really be following predicates (in practice, due to another bug, at least ia64 permits such).
2024-08-09gas: have scrubber retain more whitespaceJan Beulich7-28/+84
According to the description of the state machine, the expectation appears to be that (leaving aside labels) any insn mnemonic or directive would be followed by a comma separated list of operands. That may have been true very long ago, but the latest with the advent of more elaborate macros this isn't rhe case anymore. Neither macro parameters in macro definitions nor macro arguments in macro invocations are required to be separated by commas. Hence whitespace serves a crucial role there. Plus even without "real" macros issues exist, in e.g. .irp n, ... insn\n\(suffix) operand1, operand2 .endr Whitespace following the closing parenthesis would have been removed (ahead of even processing the .irp), as the "opcode" was deemed to have ended earlier already. Therefore, squash the distinction between "opcode" and operands, i.e. fold state 10 back into state 3. Also drop most of the distinction between "symbol chars" and "relatively normal" ones. Not entirely unexpectedly this results in the need to skip whitespace in a few more places in arch-specific code (and quite likely more changes are needed for insn forms not covered by the testsuite). As a result the D10V special case is no longer necessary. In config/tc-sparc.c also move a comment to be next to the code being commented. In opcodes/cgen-asm.in some further cleanup is done, following the local var adjustments.
2024-08-09m32r: move scrubber override to target headerJan Beulich1-0/+3
Other than LEX_IS_* settings, such #define-s don't belong into the common source file.
2024-08-09RISC-V: PR32014, .option directives shuoldn't affect elf attribute.Nelson Chu1-12/+16
The .option arch/rvc/norvc/push/pop directives can only take effect for a small/large specific code region, so they are not file-level architecture setting. They should only affect the mapping symbols only rather than the file-level elf architecture attribute. Otherwise, the elf architecture attribute will appear to missing some extensions when -flto merges files with different .option architecture settings. gas/ PR 32014 * config/tc-riscv.c (file_arch_str): New const char *, rather than the arch_str in the riscv_rps_as.subset_list, it's file-level so only be affected by .attribute arch directive. (riscv_reset_subsets_list_arch_str): Renamed to riscv_set_arch_str, and also can handle both file_arch_str and arch_str in subset_list, just give the pointer address as the input. (riscv_set_arch): Called by -march and .attribute arch, so set both file_arch_str and arch_str in subset_list. (s_riscv_option): Updated .option arch/rvc/norvc/push/pop that only set the arch_str in subset_list. (riscv_write_out_attrs): Output elf architecture attribute according to file_arch_str. Freed file_arch_str. * doc/c-riscv.texi: Added destrbution that .option directives shouldn't affect the elf attribute settings. * testsuite/gas/riscv/option-arch.s: From option-arch-01/02/03 merged. * testsuite/gas/riscv/option-arch-dis.d: Likewise, for dis-assembler. * testsuite/gas/riscv/option-arch-attr.d: Likewise, to check readelf -A.
2024-08-09gas: sparc: Fix faligndatai assembly and disassemblyRichard Henderson1-8/+9
The first operand is a general register, not an fp register; the third operand is encoded into RS2, not RS3; the second operand must match the destination operand.
2024-08-07score: drop TC_ALPHA codeJan Beulich2-24/+0
I can't see how that could ever have come into play.
2024-08-07VAX: drop OBJ_VMS leftoversJan Beulich2-55/+7
OBJ_VMS support was dropped almost 20 years ago (e330299ed5ee). Drop respective code from tc-vax.c as well. While there, make adjustments for OBJ_ELF as well: -K was dropped over 20 years ago (530556a951f5), yet left in md_shortopts. OPTION_PIC isn't really necessary either; 'k' can be used instead. And then the ELF options available weren't displayed by md_show_usage().
2024-08-06RISC-V: Add support for XCvBitmanip extension in CV32E40PMary Bennett1-0/+26
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvbitmanip` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add custom operands `Xc6` and `Xc7`. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVbitmanip as an additional ISA extension for CORE-V. * testsuite/gas/riscv/march-help.l: Add xcvbitmanip. * testsuite/gas/riscv/x-cv-bitmanip-fail.d: New Test. * testsuite/gas/riscv/x-cv-bitmanip-fail.l: New Test. * testsuite/gas/riscv/x-cv-bitmanip-fail.s: New Test. * testsuite/gas/riscv/x-cv-bitmanip.d: New Test. * testsuite/gas/riscv/x-cv-bitmanip.s: New Test. include/opcode/ChangeLog: * riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbitmanip. * riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbitmanip. (enum riscv_insn_class): Add the XCVbitmanip instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add custom operands `Xc6` and `Xc7`. * riscv-opc.c: Add XCvBitmanip instructions.
2024-08-02gas: drop unnecessary use of tc_comment_charsJan Beulich8-22/+5
The override is necessary only when a target needs other than an array of const char. For cris drop redundant sibling declarations at the same time.
2024-08-01gas: x86: ginsn: handle previously missed indirect call and jmp opsIndu Bhagat1-44/+57
Some flavors of indirect call and jmp instructions were not being handled earlier, leading to a GAS error (#1): (#1) "Error: SCFI: unhandled op 0xff may cause incorrect CFI" Not handling jmp/call (direct or indirect) ops is an error (as shown above) because SCFI needs an accurate CFG to synthesize CFI correctly. Recall that the presence of indirect jmp/call, however, does make the CFG ineligible for SCFI. In other words, generating the ginsns for them now, will eventually cause SCFI to bail out later with an error (#2) anyway: (#2) "Error: untraceable control flow for func 'XXX'" The first error (#1) gives the impression of missing functionality in GAS. So, it seems cleaner to synthesize a GINSN_TYPE_JUMP / GINSN_TYPE_CALL now in the backend, and let SCFI machinery complain with the error as expected. The handling for these indirect jmp/call instructions is similar, so reuse the code by carving out a function for the same. Adjust the testcase to include the now handled jmp/call instructions as well. gas/ * config/tc-i386-ginsn.c (x86_ginsn_indirect_branch): New function. (x86_ginsn_new): Refactor out functionality to above. gas/testsuite/ * gas/scfi/x86_64/ginsn-cofi-1.l: Adjust the output. * gas/scfi/x86_64/ginsn-cofi-1.s: Add further varieties of jmp/call opcodes.
2024-07-31x86: move ginsn stuffJan Beulich2-1102/+1123
This had been badly inserted between md_assemble() and its helpers anyway. Follow what was done for Arm64 and move the code to its own file, #include-d as appropriate.
2024-07-26microMIPS: Add MT ASE instruction set supportYunQiang Su1-1/+1
Add the MT ASE instruction operand types and encodings to the microMIPS opcode table and enable the assembly of these instructions in GAS from MIPSr2 onwards. Update the binutils and GAS testsuites accordingly. References: "MIPS Architecture for Programmers, Volume IV-f: The MIPS MT Module for the microMIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00768, Revision 1.12, July 16, 2013 Co-Authored-By: Maciej W. Rozycki <macro@redhat.com>
2024-07-26x86: accept whitespace around prefix separatorJan Beulich1-19/+30
... and prediction suffix comma. Other than documented /**/ comments currently aren't really converted to a single space, at least not for x86 in its most common configurations. That'll be fixed subsequently, at which point blanks may appear where so far none were expected. Furthermore not permitting blanks around these separators wasn't quite logical anyway - such constructs are composite ones, and hence components ought to have been permitted to be separated by whitespace from the very beginning. Furthermore note how, due to the scrubber being overly aggressive in removing whitespace, some similar construct with a prefix were already accepted. Note how certain other checks in parse_insn() can be simplified as a result. While there for the prediction suffix also make checks case-insensitive and check for a proper trailing separator.
2024-07-26x86/APX: optimize certain {nf}-form insns to BMI2 onesJan Beulich1-0/+107
..., as those leave EFLAGS untouched anyway. That's a shorter encoding, available as long as no eGPR is in use anywhere.
2024-07-19bfin: drop _ASSIGN_BANGJan Beulich2-6/+5
A few testcases demonstrate that "=!" isn't supposed to be an individual token, since "= !" is used in a number of places. So far lexing that to a single token worked because of the scrubber being overly aggressive in removing whitespace. As that's going to change, replace uses by separate ASSIGN and BANG.
2024-07-19x86: accept whitespace inside curly bracesJan Beulich1-5/+18
Other than documented /**/ comments currently aren't really converted to a single space, at least not for x86 in its most common configurations. That'll be fixed subsequently, at which point blanks may appear where so far none were expected. Furthermore not permitting blanks immediately inside curly braces wasn't quite logical anyway - such constructs are composite ones, and hence components ought to have been permitted to be separated by whitespace from the very beginning. With this we also don't care anymore whether the scrubber would remove whitespace around curly braces, so move them from extra_symbol_chars[] to operand_special_chars[]. Note: The new testcase doesn't actually exercise much (if any) of the added code. It is being put in place to ensure that subsequently, when that code actually comes into play, behavior remains the same.
2024-07-19x86: undo '{' being a symbol-start characterJan Beulich2-14/+108
Having it that way has undue side effects, in permitting not only pseudo-prefixes to be parsed correctly, but also permitting odd symbol names which ought to be possible only when quoted. Borrow what other architectures do: Put in place an "unrecognized line" hook to parse off any pseudo prefixes, while using the "start of line" hook to reject ones not actually followed by an insn. For that parsing re-use parse_insn() in yet a slightly different mode (dealing with only pseudo-prefixes). With that, pp may no longer be cleared from init_globals(), but instead needs clearing after a line was fully processed. Since md_assemble() has pretty many return paths, convert that into a local helper, with a trivial wrapper around it. Similarly pp may no longer be updated (by check_register()) when processing anything other than insn operands. To be able to (easily) recognize the case, clear current_templates.start when done with an insn (or with .insn).
2024-07-19x86: split pseudo-prefix state from i386_insnJan Beulich2-198/+199
Subsequently we will want to update that ahead of md_assemble(), with that function needing to take into account such earlier updating. Therefore it'll want resetting separately from i.
2024-07-19x86/APX: add CMPcc/CTESTcc cases to noreg64 testsJan Beulich1-11/+29
This was missed when support for the insns was added. Just like for DATA16, in rex64 neg (%rax) rex64 neg (%r16) rex64 {nf} neg (%rax) it is not logical why the last one shouldn't be permitted. Bypassing that check requires other adjustments, though, to actually properly consume (and then squash) the prefix.
2024-07-19bfin: free the allocated memoryzhangxianting1-0/+2
2024-07-19MIPS/GAS: Handle --trap command-line option dynamicallyMaciej W. Rozycki1-11/+25
We have an ISA check for the '--trap' command-line option that reports its incompatibility with the MIPS I architecture. It doesn't prevent trap instructions from being enabled though, so when attempt is made to emit one in an expansion of one of the division or multiplication macros an assertion failure triggers: .../gas/testsuite/gas/mips/brtr-opt.s: Assembler messages: .../gas/testsuite/gas/mips/brtr-opt.s:3: Error: trap exception not supported at ISA 1 .../gas/testsuite/gas/mips/brtr-opt.s:9: Warning: divide by zero .../gas/testsuite/gas/mips/brtr-opt.s:9: Internal error in macro_build at .../gas/config/tc-mips.c:9064. Please report this bug. The same assertion failure triggers without an earlier error message when the initial ISA is compatible with the '--trap', however at the time an attempt is made to emit a trap instruction from a division or multiplication macro the ISA has been changed by a '.set' pseudo-op to an incompatible one. With the way the situations are mishandled it seems unlikely that anyone relies on the current semantics and a sane approach is to decide on the fly according to the currently selected ISA as to whether to emit trap or breakpoint instructions in the case where '--trap' has been used. Change our code to do so then and clarify that in the manual, which is not explicit about how '--trap' is handled with a changing ISA. Mention the change in NEWS too since it's a applies to a user option.
2024-07-18gas: aarch64: add experimental support for SCFIIndu Bhagat3-0/+999
For synthesizing CFI (SCFI) for hand-written asm, the SCFI machinery in GAS works on the generic GAS insns (ginsns). This patch adds support in the aarch64 backend to create ginsns for a subset of the supported machine instructions. The subset includes the minimal necessary instructions to ensure SCFI correctness: - Any potential register saves and unsaves. Hence, process instructions belonging to a variety of iclasses involving str, ldr, stp, ldp. - Any change of flow instructions. This includes all conditional and unconditional branches, call (bl, blr, etc.) and return. - Most importantly, any instruction that could affect the two registers of interest: REG_SP, REG_FP. This set includes all pre-indexed and post-indexed memory operations, with writeback, on the stack. This set must also include other instructions (e.g., arithmetic insns) where the destination register is one of the afore-mentioned registers. With respect to callee-saved registers in Aarch64, FP/Advanced SIMD registers D8-D15 are included along with the relevant GPRs. Calculating offsets for loads and stores especially for Q registers needs special attention here. As an example, str q8, [sp, #16] On big-endian: STR Qn stores as a 128-bit integer (MSB first), hence, should record D8 as being saved at sp+24 rather than sp+16. On little-endian: should record D8 as being saved at sp+16 D8-D15 are the low 64 bits of Q8-Q15, and of Z8-Z15 if SVE is used; hence, they remain "interesting" for SCFI purposes in such cases. A CFI save slot always represents the low 64 bits, regardless of whether a save occurs on D, Q or Z registers. Currently, the ginsn creation machinery can handle D and Q registers on little-endian and big-endian. Apart from creating ginsn, another key responsibility of the backend is to make sure there are safeguards in place to detect and alert if an instruction of interest may have been skipped. This is done via aarch64_ginsn_unhandled () (similar to the x86 backend). This function , hence, is also intended to alert when future ISA changes may otherwise render SCFI results incorrect, because of missing ginsns for the newly added machine instructions. At this time, becuase of the complexities wrt endianness in handling Z register usage, skip sve_misc opclass altogether for now. The SCFI machinery will error out (using the aarch64_ginsn_unhandled () code path) though if Z register usage affects correctness. The current SCFI machinery does not currently synthesize the PAC-related, aarch64-specific CFI directives: .cfi_b_key_frame. The support for this is planned for near future. SCFI is enabled for ELF targets only. gas/ * config/tc-aarch64-ginsn.c: New file. * config/tc-aarch64.c (md_assemble): Include tc-aarch64-ginsn.c file. Invoke aarch64_ginsn_new. * config/tc-aarch64.h (TARGET_USE_GINSN): Define for SCFI enablement. (TARGET_USE_SCFI): Likewise. (SCFI_MAX_REG_ID): New definition. (REG_FP): Likewise. (REG_LR): Likewise. (REG_SP): Likewise. (SCFI_INIT_CFA_OFFSET): Likewise. (SCFI_CALLEE_SAVED_REG_P): Likewise. (aarch64_scfi_callee_saved_p): New declaration.
2024-07-13Revert "MIPS/GAS: Omit LI 0 for condition trap"Maciej W. Rozycki1-8/+3
This reverts commit bfa257b407270d1c808b31fbd97da779e0fd20d2. It was applied unapproved.
2024-07-12aarch64: Add support for sme2.1 movaz instructions.Srinath Parvathaneni1-0/+1
This patch adds support for following sme2.1 movaz instructions and the spec is available here [1]. 1. MOVAZ (array to vector, two registers). 2. MOVAZ (array to vector, four registers). 3. MOVAZ (tile to vector, single). [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en
2024-07-12x86/APX: remove two inconsistenciesJan Beulich1-18/+23
As indicated in earlier discussion, permitting GOTTPOFF uniformly for all legacy non-SIMD insns while at the same time restricting to just certain ADD forms when EVEX-encoded is inconsistent. Make promoted insns "equal" to their legacy original ones. Doing that adjustment prevents another inconsistency, too: In data16 neg (%rax) data16 neg (%r16) data16 {nf} neg (%rax) it is not logical why the last one shouldn't be permitted. Bypassing that check requires other adjustments, though, to actually properly consume (and then squash) the data size prefix. While there also add the missing CMP and TEST cases to the test case being modified.
2024-07-12x86/APX: correct TEST/CTESTcc with 1st operand being a memory oneJan Beulich1-4/+8
While they properly inherited D and C, code processing the reversal of operands wasn't updated accordingly (and "reversed" operands also weren't tested anywhere).
2024-07-12MIPS/GAS: Omit LI 0 for condition trapYunQiang Su1-3/+8
MIPSr6 removes condition trap instructions with imm, so we expand the instruction like "tne $2,IMM" to li $at,IMM tne $2,$at While if IMM is 0, we can use tne $2,$zero only.
2024-07-12aarch64: disable feature b16b16Matthieu Longo1-1/+3
Feature b16b16 is currently incomplete and requires re-work. Disable the command line option for b16b16, and mark the associated tests as XFAIL.
2024-07-08aarch64: Add support for sve2p1 pmov instruction.srinath1-3/+25
This patch adds support for followign SVE2p1 instruction, spec is available here [1]. 1. PMOV (to vector) 2. PMOV (to predicate) Both pmov (to vector) and pmov (to predicate) have destination scalable vector register and source scalable vector register respectively as an operand with no suffix and optional index. To handle this case we have added 8 new operands in this patch. AARCH64_OPND_SVE_Zn0_INDEX, /* Zn[index], bits [9:5]. */ AARCH64_OPND_SVE_Zn1_17_INDEX, /* Zn[index], bits [9:5,17]. */ AARCH64_OPND_SVE_Zn2_18_INDEX, /* Zn[index], bits [9:5,18:17]. */ AARCH64_OPND_SVE_Zn3_22_INDEX, /* Zn[index], bits [9:5,18:17,22]. */ AARCH64_OPND_SVE_Zd0_INDEX, /* Zn[index], bits [4:0]. */ AARCH64_OPND_SVE_Zd1_17_INDEX, /* Zn[index], bits [4:0,17]. */ AARCH64_OPND_SVE_Zd2_18_INDEX, /* Zn[index], bits [4:0,18:17]. */ AARCH64_OPND_SVE_Zd3_22_INDEX, /* Zn[index], bits [4:0,18:17,22]. */ Since the index of the <Zd> operand is optional, the index part is dropped in disassembly in both the cases of "no index" or "zero index". As per spec: PMOV <Zd>{[<imm>]}, <Pn>.D PMOV <Pn>.D, <Zd>{[<imm>]} Example1: Assembly: pmov z5[0], p6.d Disassembly: pmov z5, p6.d Assembly: pmov z5, p6.d Disassembly: pmov z5, p6.d Example2: Assembly: pmov p4.b, z5[0] Disassembly: pmov p4.b, z5 Assembly: pmov p4.b, z5 Disassembly: pmov p4.b, z5 [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
2024-07-05x86-64: Fix support for APX NF TLS IE with 2 operandsLingling Kong1-3/+2
Added the restriction in assemble for APX TLS IE that the destination can only be a register. gas/ * config/tc-i386.c (md_assemble): Added stricter restrictions for APX TLS IE.
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