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AgeCommit message (Expand)AuthorFilesLines
2021-12-28gas reloc sortingAlan Modra3-41/+2
2021-12-24RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta1-5/+5
2021-12-21x86: -mfence-as-lock-add=yes doesn't work for 16-bit modeJan Beulich1-1/+6
2021-12-21gas/ELF: avoid below-base ref in obj_elf_parse_section_letters()Jan Beulich1-13/+11
2021-12-16Fix AVR assembler so that it creates relocs that will work with linker relaxa...Nick Clifton2-0/+29
2021-12-16arm: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford1-1/+11
2021-12-16arm: Add support for Armv8.7-A and Armv8.8-ARichard Sandiford1-0/+7
2021-12-16aarch64: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford1-0/+3
2021-12-15loongarch64 build failure on 32-bit hostAlan Modra1-6/+6
2021-12-02aarch64: Add BC instructionRichard Sandiford1-0/+2
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford1-10/+28
2021-12-02aarch64: Add support for +mopsRichard Sandiford1-0/+33
2021-12-02aarch64: Add support for Armv8.8-ARichard Sandiford1-0/+1
2021-12-02aarch64: Provide line info for unclosed sequencesRichard Sandiford2-12/+14
2021-11-30aarch64: Check for register aliases before mnemonicsRichard Sandiford1-33/+29
2021-11-22RISC-V: Replace .option rvc/norvc with .option arch, +c/-c.Nelson Chu1-0/+4
2021-11-19RISC-V: Support new .option arch directive.Nelson Chu1-17/+40
2021-11-19RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC.Nelson Chu2-0/+59
2021-11-18RISC-V: Add instructions and operand set for z[fdq]inxjiawei1-1/+3
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus1-0/+78
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus1-8/+48
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus1-8/+107
2021-11-17aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus1-0/+104
2021-11-17aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus1-1/+218
2021-11-17aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus1-1/+126
2021-11-17aarch64: [SME] Add +sme option to -marchPrzemyslaw Wirkus1-0/+11
2021-11-17RISC-V: Support rvv extension with released version 1.0.Nelson Chu1-11/+409
2021-11-16x86: Don't allow KMOV in TLS code sequencesH.J. Lu1-5/+19
2021-11-16RISC-V: Scalar crypto instructions and operand set.jiawei1-0/+29
2021-11-15PowerPC64 @notoc in non-power10 codeAlan Modra1-0/+7
2021-11-11RISC-V: Dump objects according to the elf architecture attribute.Nelson Chu1-87/+23
2021-11-10arm: enable Cortex-A710 CPUPrzemyslaw Wirkus1-0/+5
2021-11-10PR 28447: implement multiple parameters for .file on XCOFFClément Chigot2-1/+64
2021-11-06Modernise yyerrorAlan Modra1-2/+5
2021-11-04RISC-V: Clarify the behavior of .option rvc or norvc.Nelson Chu1-21/+18
2021-11-01arm: add armv9-a architecture to -marchPrzemyslaw Wirkus1-3/+20
2021-10-28ARM assembler: Allow up to 32 single precision registers in the VPUSH and VPO...Markus Klein1-17/+23
2021-10-28arm: add unwinder encoding support for PACBTITejas Belagod1-5/+57
2021-10-27RISC-V: Tidy riscv assembler and disassembler.Nelson Chu1-288/+304
2021-10-25x86: Also handle stores for -muse-unaligned-vector-moveH.J. Lu1-3/+5
2021-10-24LoongArch gas supportliuzhensong6-0/+2029
2021-10-22x86: Add -muse-unaligned-vector-move to assemblerH.J. Lu1-0/+39
2021-10-07RISC-V: Add support for Zbs instructionsPhilipp Tomsich1-0/+3
2021-09-30arm: enable Cortex-R52+ CPUPrzemyslaw Wirkus1-0/+3
2021-09-30aarch64: Enable Cortex-X2 CPUPrzemyslaw Wirkus1-0/+6
2021-09-30aarch64: Enable Cortex-A710 CPUPrzemyslaw Wirkus1-0/+6
2021-09-30aarch64: Enable Cortex-A510 CPUPrzemyslaw Wirkus1-0/+6
2021-09-30aarch64: add armv9-a architecture to -marchPrzemyslaw Wirkus1-0/+1
2021-09-22dwarf2 sub-section testAlan Modra1-2/+5
2021-09-17RISC-V: Merged extension string tables and their version tables into one.Nelson Chu1-119/+7
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