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AgeCommit message (Expand)AuthorFilesLines
2018-01-02Fix typo in do_mrs function in ARM assembler.Nick Clifton1-1/+1
2017-12-20RISC-V: Add compressed instruction hints, and a few misc cleanups.Jim Wilson1-0/+3
2017-12-19Correct disassembly of dot product instructions.Tamar Christina1-2/+8
2017-12-19Add support for V_4B so we can properly reject it.Tamar Christina1-3/+3
2017-12-18Resolve PR 22493 - the encoding to be used when pushing the stack pointer ont...Nick Clifton1-0/+5
2017-12-18x86: fold certain AVX and AVX2 templatesJan Beulich1-38/+43
2017-12-18x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich2-80/+83
2017-12-18x86: drop FloatReg and FloatAccJan Beulich1-11/+8
2017-12-18x86: replace Reg8, Reg16, Reg32, and Reg64Jan Beulich2-133/+118
2017-12-17x86: Check pseudo prefix without instructionH.J. Lu1-0/+6
2017-12-15x86: correct operand type checksJan Beulich1-4/+4
2017-12-15x86: correct abort checkJan Beulich1-2/+2
2017-12-14Update the address of the FSF in the copyright notice of files which were usi...Nick Clifton6-18/+18
2017-12-12Don't mask X_add_number containing a register numberAlan Modra1-1/+1
2017-12-08gas: xtensa: fix comparison of trampoline chain symbolsMax Filippov1-4/+22
2017-12-01Use consistent types for holding instructions, instruction masks, etc.Peter Bergner1-32/+32
2017-11-30x86: drop Vec_Disp8Jan Beulich1-54/+16
2017-11-30x86/Intel: issue diagnostics for redundant segment override prefixesJan Beulich1-3/+26
2017-11-30Revert "x86: Update segment register check in Intel syntax"Jan Beulich1-1/+7
2017-11-29Fix riscv malloc error on small alignment after norvc.Jim Wilson1-2/+10
2017-11-29[GAS][AARCH64]Fix a typo for IP1 register alias.Renlin Li1-1/+1
2017-11-29Use the record_alignment function when creating a .note section, in case the ...Nick Clifton1-1/+1
2017-11-27Compress loads/stores with implicit 0 offset.Jim Wilson1-6/+32
2017-11-27gas: xtensa: speed up find_trampoline_segMax Filippov1-1/+8
2017-11-27gas: xtensa: implement trampoline coalescingMax Filippov1-12/+274
2017-11-27gas: xtensa: reuse trampoline placement codeMax Filippov1-88/+9
2017-11-27gas: xtensa: rewrite xg_relax_trampolineMax Filippov2-285/+236
2017-11-27gas: xtensa: merge trampoline_frag into xtensa_frag_typeMax Filippov2-67/+61
2017-11-27gas: xtensa: reuse find_trampoline_segMax Filippov1-22/+16
2017-11-27gas: xtensa: extract jump assembling for trampolinesMax Filippov1-102/+57
2017-11-27gas: extract xg_relax_trampoline from xtensa_relax_fragMax Filippov1-159/+168
2017-11-27When creating a .note section to contain a version note, set the section alig...Nick Clifton1-0/+1
2017-11-24x86: reject further invalid AVX-512 masking constructsJan Beulich1-3/+9
2017-11-23Fix build error with --enable-targets=all.Jim Wilson1-0/+3
2017-11-23x86: fix AVX-512 16-bit addressingJan Beulich1-5/+1
2017-11-23x86-64: always use unsigned 32-bit reloc for 32-bit addressing w/o base regJan Beulich1-2/+2
2017-11-23x86: drop redundant VSIB handling codeJan Beulich1-7/+1
2017-11-23x86/Intel: don't report multiple errors for a single insn operandJan Beulich1-2/+4
2017-11-22Riscv ld-elf/stab failure and fake label cleanup.Jim Wilson1-0/+3
2017-11-22[GAS/ARM] Clarify relation between reg_expected_msgs and arm_reg_typeThomas Preud'homme1-23/+26
2017-11-21xtensa error messageAlan Modra1-16/+6
2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina1-0/+3
2017-11-16ix86/Intel: don't require memory operand size specifier for PTWRITEJan Beulich1-1/+1
2017-11-15Separate the new FP16 instructions backported from Armv8.4-a to Armv8.2-a int...Tamar Christina1-1/+8
2017-11-13gas/arm64: don't emit stack pointer symbol table entriesJan Beulich1-5/+6
2017-11-13x86: don't default variable shift count insns to 8-bit operand sizeJan Beulich1-1/+2
2017-11-13x86/Intel: don't mistake riz/eiz as base registerJan Beulich1-1/+3
2017-11-13x86-64/Intel: issue diagnostic for out of range displacementJan Beulich2-29/+42
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina1-0/+8
2017-11-09Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options...Tamar Christina1-0/+6
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