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6 daysx86: drop largely defunct gas emulationsJan Beulich1-0/+2
Both ELF and COFF have various sub-flavors, each of which would then require its own emulation: Right now when configuring a COFF/PE secondary target (with perhaps an ELF primary one), one gets plain COFF emulation rather than COFF/PE one. As such a multitude of emulations would be unwieldy (and likely fragile) drop gas emulations altogether instead.
2024-09-25RISC-V: Add Smrnmi extension csrs.Jiawei1-2/+2
This patch support Smrnmi extension[1], The csrs address can be find in[2]. [1] https://github.com/riscv/riscv-isa-manual/commit/35eb3948bf0b87c83fab5a7238bd68b6211faf62 [2] https://github.com/riscv/riscv-isa-manual/blob/smrnmi-1.0/src/priv-csrs.adoc bfd/ChangeLog: * elfxx-riscv.c: New extension. gas/ChangeLog: * NEWS: Add Smrnmi extension support. * config/tc-riscv.c (enum riscv_csr_class): New extension class. (riscv_csr_address): Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New csrs. * testsuite/gas/riscv/csr-version-1p10.l: Ditto. * testsuite/gas/riscv/csr-version-1p11.d: Ditto. * testsuite/gas/riscv/csr-version-1p11.l: Ditto. * testsuite/gas/riscv/csr-version-1p12.d: Ditto. * testsuite/gas/riscv/csr-version-1p12.l: Ditto. * testsuite/gas/riscv/csr.s: Ditto. * testsuite/gas/riscv/march-help.l: New extension. include/ChangeLog: * opcode/riscv-opc.h (CSR_MNSCRATCH): New csr. (CSR_MNEPC): Ditto. (CSR_MNCAUSE): Ditto. (CSR_MNSTATUS): Ditto. (DECLARE_CSR): New csr declarations.
2024-09-03RISC-V: Add support for XCVsimd extension in CV32E40PMary Bennett1-2/+2
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvsimd` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * NEWS: Updated. * config/tc-riscv.c (validate_riscv_insn): Add custom operands. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVsimd as an additional ISA extension for CORE-V. * testsuite/gas/riscv/march-help.l: Add xcvsimd. * testsuite/gas/riscv/x-cv-simd.d: New test. * testsuite/gas/riscv/x-cv-simd.s: New test. * testsuite/gas/riscv/x-cv-simd-fail.d: New test. * testsuite/gas/riscv/x-cv-simd-fail.l: New test. * testsuite/gas/riscv/x-cv-simd-fail.s: New test. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVsimd. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVsimd. (enum riscv_insn_class): Add the XCVsimd instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add custom operands. * riscv-opc.c: Add XCVsimd instructions.
2024-08-27RISC-V: PR32036, Support Zcmp cm.mva01s and cm.mvsa01 instructions.Jiawei1-1/+2
This patch supports Zcmp instruction 'cm.mva01s' and 'cm.mvsa01'. All disassemble instructions use the sreg format. Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> gas/ChangeLog: PR 32036 * NEWS: Updated. * config/tc-riscv.c (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/zcmp-mv.d: New test. * testsuite/gas/riscv/zcmp-mv.s: New test. include/ChangeLog: PR 32036 * opcode/riscv-opc.h (MATCH_CM_MVA01S): New opcode. (MASK_CM_MVA01S): New mask. (MATCH_CM_MVSA01): New opcode. (MASK_CM_MVSA01): New mask. (DECLARE_INSN): New declarations. * opcode/riscv.h (OP_MASK_SREG1): New mask. (OP_SH_SREG1): New operand code. (OP_MASK_SREG2): New mask. (OP_SH_SREG2): New operand code. (X_A0): New reg number. (X_A1): Ditto. (X_S7): Ditto. (RISCV_SREG_0_7): New macro function. opcodes/ChangeLog: PR 32036 * riscv-dis.c (riscv_zcmp_get_sregno): New function. (print_insn_args): New operators. * riscv-opc.c (match_sreg1_not_eq_sreg2): New match function.
2024-08-12Revert "gas: have scrubber retain more whitespace"H.J. Lu1-7/+0
This reverts commit 6ae8a30d44f016cafb46a75843b5109316eb1996. This fixes PR gas/32073.
2024-08-09gas: have scrubber retain more whitespaceJan Beulich1-0/+7
According to the description of the state machine, the expectation appears to be that (leaving aside labels) any insn mnemonic or directive would be followed by a comma separated list of operands. That may have been true very long ago, but the latest with the advent of more elaborate macros this isn't rhe case anymore. Neither macro parameters in macro definitions nor macro arguments in macro invocations are required to be separated by commas. Hence whitespace serves a crucial role there. Plus even without "real" macros issues exist, in e.g. .irp n, ... insn\n\(suffix) operand1, operand2 .endr Whitespace following the closing parenthesis would have been removed (ahead of even processing the .irp), as the "opcode" was deemed to have ended earlier already. Therefore, squash the distinction between "opcode" and operands, i.e. fold state 10 back into state 3. Also drop most of the distinction between "symbol chars" and "relatively normal" ones. Not entirely unexpectedly this results in the need to skip whitespace in a few more places in arch-specific code (and quite likely more changes are needed for insn forms not covered by the testsuite). As a result the D10V special case is no longer necessary. In config/tc-sparc.c also move a comment to be next to the code being commented. In opcodes/cgen-asm.in some further cleanup is done, following the local var adjustments.
2024-08-07gas/NEWS: Moved RISC-V Zimop/Zcmop changes into 2.43 section due to backport.Nelson Chu1-2/+2
2024-08-06RISC-V: Add support for XCvBitmanip extension in CV32E40PMary Bennett1-0/+2
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvbitmanip` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add custom operands `Xc6` and `Xc7`. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVbitmanip as an additional ISA extension for CORE-V. * testsuite/gas/riscv/march-help.l: Add xcvbitmanip. * testsuite/gas/riscv/x-cv-bitmanip-fail.d: New Test. * testsuite/gas/riscv/x-cv-bitmanip-fail.l: New Test. * testsuite/gas/riscv/x-cv-bitmanip-fail.s: New Test. * testsuite/gas/riscv/x-cv-bitmanip.d: New Test. * testsuite/gas/riscv/x-cv-bitmanip.s: New Test. include/opcode/ChangeLog: * riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbitmanip. * riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbitmanip. (enum riscv_insn_class): Add the XCVbitmanip instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add custom operands `Xc6` and `Xc7`. * riscv-opc.c: Add XCvBitmanip instructions.
2024-08-06RISC-V: Add support for Zcmop extensionXiao Zeng1-1/+1
This implements the Zcmop (Compressed Zimop) extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc> The Zcmop extension requires the Zca extension. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zcmop. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zcmop.d: New test. * testsuite/gas/riscv/zcmop.s: New test. include/ChangeLog: * opcode/riscv-opc.h (DECLARE_INSN): New declarations for Zcmop. (MATCH_C_MOP_1, MATCH_C_MOP_3, MATCH_C_MOP_5, MATCH_C_MOP_7, MATCH_C_MOP_9, MATCH_C_MOP_11, MATCH_C_MOP_13, MATCH_C_MOP_15): Define. (MASK_C_MOP_1, MASK_C_MOP_3, MASK_C_MOP_5, MASK_C_MOP_7, MASK_C_MOP_9, MASK_C_MOP_11, MASK_C_MOP_13, MASK_C_MOP_15): Ditto. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZCMOP. opcodes/ChangeLog: * riscv-opc.c: Add Zcmop instructions.
2024-08-06RISC-V: Add support for Zimop extensionXiao Zeng1-0/+2
This implements the Zimop (May-Be-Operations) extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zimop (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zimop.d: New test. * testsuite/gas/riscv/zimop.s: New test. include/ChangeLog: * opcode/riscv-opc.h (DECLARE_INSN): New declarations for Zimop. (MATCH_MOP_R_0, MATCH_MOP_R_1, MATCH_MOP_R_2, MATCH_MOP_R_3, MATCH_MOP_R_4, MATCH_MOP_R_5, MATCH_MOP_R_6, MATCH_MOP_R_7, MATCH_MOP_R_8, MATCH_MOP_R_9, MATCH_MOP_R_10, MATCH_MOP_R_11, MATCH_MOP_R_12, MATCH_MOP_R_13, MATCH_MOP_R_14, MATCH_MOP_R_15, MATCH_MOP_R_16, MATCH_MOP_R_17, MATCH_MOP_R_18, MATCH_MOP_R_19, MATCH_MOP_R_20, MATCH_MOP_R_21, MATCH_MOP_R_22, MATCH_MOP_R_23, MATCH_MOP_R_24, MATCH_MOP_R_25, MATCH_MOP_R_26, MATCH_MOP_R_27, MATCH_MOP_R_28, MATCH_MOP_R_29, MATCH_MOP_R_30, MATCH_MOP_R_31, MATCH_MOP_RR_0, MATCH_MOP_RR_1, MATCH_MOP_RR_2, MATCH_MOP_RR_3, MATCH_MOP_RR_4, MATCH_MOP_RR_5, MATCH_MOP_RR_6, MATCH_MOP_RR_7): Define. (MASK_MOP_R_0, MASK_MOP_R_1, MASK_MOP_R_2, MASK_MOP_R_3, MASK_MOP_R_4, MASK_MOP_R_5, MASK_MOP_R_6, MASK_MOP_R_7, MASK_MOP_R_8, MASK_MOP_R_9, MASK_MOP_R_10, MASK_MOP_R_11, MASK_MOP_R_12, MASK_MOP_R_13, MASK_MOP_R_14, MASK_MOP_R_15, MASK_MOP_R_16, MASK_MOP_R_17, MASK_MOP_R_18, MASK_MOP_R_19, MASK_MOP_R_20, MASK_MOP_R_21, MASK_MOP_R_22, MASK_MOP_R_23, MASK_MOP_R_24, MASK_MOP_R_25, MASK_MOP_R_26, MASK_MOP_R_27, MASK_MOP_R_28, MASK_MOP_R_29, MASK_MOP_R_30, MASK_MOP_R_31, MASK_MOP_RR_0, MASK_MOP_RR_1, MASK_MOP_RR_2, MASK_MOP_RR_3, MASK_MOP_RR_4, MASK_MOP_RR_5, MASK_MOP_RR_6, MASK_MOP_RR_7): Ditto. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZIMOP. opcodes/ChangeLog: * riscv-opc.c: Add Zimop instructions.
2024-07-30gas/NEWS, ld/NEWS: Announce LoongArch changes in 2.43Lulu Cai1-0/+3
2024-07-20Add markers for 2.43 branch/releaseNick Clifton1-0/+2
2024-07-19MIPS/GAS: Handle --trap command-line option dynamicallyMaciej W. Rozycki1-0/+7
We have an ISA check for the '--trap' command-line option that reports its incompatibility with the MIPS I architecture. It doesn't prevent trap instructions from being enabled though, so when attempt is made to emit one in an expansion of one of the division or multiplication macros an assertion failure triggers: .../gas/testsuite/gas/mips/brtr-opt.s: Assembler messages: .../gas/testsuite/gas/mips/brtr-opt.s:3: Error: trap exception not supported at ISA 1 .../gas/testsuite/gas/mips/brtr-opt.s:9: Warning: divide by zero .../gas/testsuite/gas/mips/brtr-opt.s:9: Internal error in macro_build at .../gas/config/tc-mips.c:9064. Please report this bug. The same assertion failure triggers without an earlier error message when the initial ISA is compatible with the '--trap', however at the time an attempt is made to emit a trap instruction from a division or multiplication macro the ISA has been changed by a '.set' pseudo-op to an incompatible one. With the way the situations are mishandled it seems unlikely that anyone relies on the current semantics and a sane approach is to decide on the fly according to the currently selected ISA as to whether to emit trap or breakpoint instructions in the case where '--trap' has been used. Change our code to do so then and clarify that in the manual, which is not explicit about how '--trap' is handled with a changing ISA. Mention the change in NEWS too since it's a applies to a user option.
2024-07-18X86: Update gas/NEWS for Intel APX.Cui, Lili1-1/+1
gas/ChangeLog: * NEWS: Added "APX_F is fully supportted" to gas/NEWS.
2024-07-11X86: Update gas/NEWS for Intel APX.Cui, Lili1-0/+6
gas/ChangeLog: * NEWS: Update gas/NEWS for Intel APX.
2024-07-10Add support for a .base64 pseudo-op to gasNick Clifton1-0/+3
PR 31964
2024-06-28aarch64: Add support for Armv9.5-A architectureClaudio Bantaloukas1-0/+2
The new -march=armv9.5-a flag enables access to the mandatory cpa, lut and faminmax extensions. Existing test cases for features are extended to verify they work without additional flags.
2024-06-24gas, aarch64: Add SME2 lutv2 extensionsaurabh.jha@arm.com1-0/+2
Introduces instructions for the SME2 lutv2 extension for AArch64. They are documented in the following document: * ARM DDI0602 For both luti4 instructions, we introduced an operand called SME_Znx2_BIT_INDEX. We use the existing function parse_vector_reg_list for parsing but modified that function so that it can accept operands without qualifiers and rejects instructions that have operands with qualifiers but are not supposed to have operands with qualifiers. For disassembly, we modified print_register_list so that it could accept register lists without qualifiers. For one luti4 instruction, we introduced a SME_Zdnx4_STRIDED. It is similar to SME_Ztx4_STRIDED and we could use existing code for parsing, encoding, and disassembly. For movt instruction, we introduced an operand called SME_ZT0_INDEX2_12. This is a ZT0 register with a bit index encoded in [13:12]. It is similar to SME_ZT0_INDEX. We also introduced an iclass named sme_size_12_b so that we can encode size bits [13:12] correctly when only 'b' is allowed as qualifier.
2024-06-18RISC-V: Updated gas/NEWS and gas/doc/c-riscv.texi for vendor extensions.Nelson Chu1-0/+5
gas/ * NEWS: Updated for XCvMem, XCvBi, XCvElw, XSfCease. * doc/c-riscv.texi: Minor typo for XCv* extensions.
2024-06-18RISC-V: Support Zacas extension.Gianluca Guida1-0/+2
https://github.com/riscvarchive/riscv-zacas/releases/tag/v1.0 The Zacas extension introduce compare-and-swap instructions to operate on 32-bit, 64-bit and 128-bit (RV64 only) data values. It introduces three new instructions: - amocas.w (32-bit CAS) - amocas.d (64-bit CAS) - amocas.q (128-bit CAS, RV64 only) Like other AMOs in the A extension, Zacas instructions have '.aq', '.rl' and '.aqrl' variations. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): 'A' implied by 'Zacas'. (riscv_supported_std_z_ext): Add 'Zacas' extension. (riscv_multi_subset_supports, riscv_multi_subset_supports_ext): Handle INSN_CLASS_ZACAS case. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Updated. * testsuite/gas/riscv/zacas-32.d: New test (RV32). * testsuite/gas/riscv/zacas-fail-32.d: Likewise. * testsuite/gas/riscv/zacas-64.d: New test (RV64). * testsuite/gas/riscv/zacas-fail-64.d: Likewise. * testsuite/gas/riscv/zacas.s: New test source. * testsuite/gas/riscv/zacas-fail.s: Likewise. * testsuite/gas/riscv/zacas-fail-32.l: New file. * testsuite/gas/riscv/zacas-fail-64.l: Likewise. include/ChangeLog: * include/opcode/riscv.h (INSN_CLASS_ZACAS): New definition. * include/opcode/riscv-opc.h (MATCH_AMOCAS_W, MASK_AMOCAS_W) (MATCH_AMOCAS_D, MASK_AMOCAS_D, MATCH_AMOCAS_Q, MASK_AMOCAS_Q): Likewise. (amocas_w, amocas_d, amocas_q): Declare instructions. opcodes/ChangeLog: * riscv-opc.c (match_rs2_rd_even): New function. (amocas_w, amocas_d, amocas_q, amocas_w.aq) (amocas_d.aq, amocas_q.aq, amocas_w.rl, amocas_d.rl, amocas_q.rl) (amocas_w.aqrl, amocas_d.aqrl, amocas_q.aqrl): Add instructions.
2024-06-12RISC-V: Support S[sm]csrind extension csrs.Jiawei1-0/+2
This patch supports RISC-V Smcsrind/Sscsrind privilege extension csrs. Reuse csr 'smselect/siselect', 'mireg/sireg' and 'vsiselect,vsireg' csrs in Smaia/Ssaia extension. bfd/ChangeLog: * elfxx-riscv.c: New extensions. gas/ChangeLog: * NEWS: Updated. * config/tc-riscv.c (enum riscv_csr_class): New extensions. (riscv_csr_address): Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New csrs. * testsuite/gas/riscv/csr-version-1p10.l: Ditto. * testsuite/gas/riscv/csr-version-1p11.d: Ditto. * testsuite/gas/riscv/csr-version-1p11.l: Ditto. * testsuite/gas/riscv/csr-version-1p12.d: Ditto. * testsuite/gas/riscv/csr-version-1p12.l: Ditto. * testsuite/gas/riscv/csr.s: Ditto. * testsuite/gas/riscv/march-help.l: New extensions. include/ChangeLog: * opcode/riscv-opc.h (CSR_MIREG2): New csr. (CSR_MIREG3): Ditto. (CSR_MIREG4): Ditto. (CSR_MIREG5): Ditto. (CSR_MIREG6): Ditto. (CSR_SIREG2): Ditto. (CSR_SIREG3): Ditto. (CSR_SIREG4): Ditto. (CSR_SIREG5): Ditto. (CSR_SIREG6): Ditto. (CSR_VSIREG2): Ditto. (CSR_VSIREG3): Ditto. (CSR_VSIREG4): Ditto. (CSR_VSIREG5): Ditto. (CSR_VSIREG6): Ditto. (DECLARE_CSR): Ditto.
2024-06-10gas: extend \+ support to .reptJan Beulich1-2/+2
PR gas/31752 While not quite as macro-like as .irp / .irpc, this perhaps benefits from supporting \+ even more than those: It allows, where desired, to get away without maintaining an explicit count variable in source code. Keep .rep (and custom per-arch uses of s_rept() / do_repeat()) behavior unaltered.
2024-06-06RISC-V: Add support for Zvfbfwma extensionXiao Zeng1-0/+2
This implements the Zvfbfwma extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfwma---vector-bf16-widening-mul-add> 1 In spec: "Zvfbfwma requires the Zvfbfmin extension and the Zfbfmin extension." 1.1 In Embedded Processor: Zvfbfwma -> Zvfbfmin -> Zve32f 1.2 In Application Processor: Zvfbfwma -> Zvfbfmin -> V 1.3 In both scenarios, there are: Zvfbfwma -> Zfbfmin 2 Depending on different usage scenarios, the Zvfbfwma extension may depend on 'V' or 'Zve32f'. This patch only implements dependencies in scenario of Embedded Processor. This is consistent with the processing strategy in Zvfbfmin. In scenario of Application Processor, it is necessary to explicitly indicate the dependent 'V' extension. For relevant information in gcc, please refer to: <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=38dd4e26e07c6be7cf4d169141ee4f3a03f3a09d> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfwma. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zvfbfwma.d: New test. * testsuite/gas/riscv/zvfbfwma.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VFWMACCBF16_VF): Define. (MASK_VFWMACCBF16_VF): Ditto. (MATCH_VFWMACCBF16_VV): Ditto. (MASK_VFWMACCBF16_VV): Ditto. (DECLARE_INSN): New declarations for Zvfbfwma. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZVFBFWMA opcodes/ChangeLog: * riscv-opc.c: Add Zvfbfwma instructions.
2024-06-06RISC-V: Add support for Zvfbfmin extensionXiao Zeng1-0/+2
This implements the Zvfbfmin extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfmin---vector-bf16-converts> Depending on different usage scenarios, the Zvfbfmin extension may depend on 'V' or 'Zve32f'. This patch only implements dependencies in scenario of Embedded Processor. In scenario of Application Processor, it is necessary to explicitly indicate the dependent 'V' extension. For relevant information in gcc, please refer to: <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=1ddf65c5fc6ba7cf5826e1c02c569c923a541c09> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfmin. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zvfbfmin.d: New test. * testsuite/gas/riscv/zvfbfmin.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W): Define. (MASK_VFNCVTBF16_F_F_W): Ditto. (MATCH_VFWCVTBF16_F_F_V): Ditto. (MASK_VFWCVTBF16_F_F_V): Ditto. (DECLARE_INSN): New declarations for Zvfbfmin. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZVFBFMIN opcodes/ChangeLog: * riscv-opc.c: Add Zvfbfmin instructions.
2024-06-06RISC-V: Add support for Zfbfmin extensionXiao Zeng1-0/+2
This implements the Zfbfmin extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zfbfmin---scalar-bf16-converts> 1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and FMV.H.X instructions as defined in the Zfh extension. 2 The Zfhmin extension includes the following instructions from the Zfh extension: FLH, FSH, FMV.X.H, FMV.H.X... View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zfh.adoc> 3 Zfhmin extension depend on 'F'. 4 Simply put, just make Zfbfmin dependent on Zfhmin. Perhaps in the future, we could propose making the FLH, FSH, FMV.X.H, and FMV.H.X instructions an independent extension to achieve precise dependency relationships for the Zfbfmin. 5 For relevant information in gcc, please refer to: <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=35224ead63732a3550ba4b1332c06e9dc7999c31> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zfbfmin. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zfbfmin.d: New test. * testsuite/gas/riscv/zfbfmin.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_FCVT_BF16_S): Define. (MASK_FCVT_BF16_S): Ditto. (MATCH_FCVT_S_BF16): Ditto. (MASK_FCVT_S_BF16): Ditto. (DECLARE_INSN): New declarations for Zfbfmin. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZFBFMIN. opcodes/ChangeLog: * riscv-opc.c: Add Zfbfmin instructions.
2024-05-29x86/Intel: warn about undue mnemonic suffixesJan Beulich1-0/+3
Except for very few insns mnemonic suffixes aren't permitted in Intel syntax. Warn about such for now, indicating that they will be outright refused down the road. While fiddling with testcases to address fallout, drop a few things which should never have been tested as valid Intel syntax. Also add a previously missing line to simd-suffix.d.
2024-05-28gas, aarch64: Add AdvSIMD lut extensionsaurabh.jha@arm.com1-0/+2
Introduces instructions for the Advanced SIMD lut extension for AArch64. They are documented in the following links: * luti2: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI2--Lookup-table-read-with-2-bit-indices-?lang=en * luti4: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI4--Lookup-table-read-with-4-bit-indices-?lang=en These instructions needed definition of some new operands. We will first discuss operands for the third operand of the instructions and then discuss a vector register list operand needed for the second operand. The third operands are vectors with bit indices and without type qualifiers. They are called Em_INDEX1_14, Em_INDEX2_13, and Em_INDEX3_12 and they have 1 bit, 2 bit, and 3 bit indices respectively. For these new operands, we defined new parsing case branch. The lsb and width of these operands are the same as many existing but the convention is to give different names to fields that serve different purpose so we introduced new fields in aarch64-opc.c and aarch64-opc.h for these new operands. For the second operand of these instructions, we introduced a new operand called LVn_LUT. This represents a vector register list with stride 1. We defined new inserter and extractor for this new operand and it is encoded in FLD_Rn. We are enforcing the number of registers in the reglist using opcode flag rather than operand flag as this is what other SIMD vector register list operands are doing. The disassembly also uses opcode flag to print the correct number of registers.
2024-05-24gas: extend \+ support to .irp / .irpcJan Beulich1-3/+4
PR gas/31752 These are effectively macro-like, without any separate macro definition. They already support \@, so they would better also support \+. This allows, where desired, to get away without maintaining an explicit count variable in source code. With this the recently introduced testcase doesn't need any xfails anymore.
2024-05-13Add new assembler macro pseudo-variable \+ which counts the number of times ↵Nick Clifton1-0/+4
a macro has been invoked.
2024-04-09RISC-V: Support Zcmp push/pop instructions.Jiawei1-0/+2
Support zcmp extension push/pop/popret and popret zero instructions. The `reg_list' is a list containing 1 to 13 registers, we can use: "{ra}, {ra, s0}, {ra, s0-s1}, {ra, s0-s2} ... {ra, s0-sN}" to present this feature. Passed gcc/binutils regressions of riscv-gnu-toolchain. Most of work was finished by Sinan Lin. Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subset): Imply zca for zcmp. (riscv_supported_std_z_ext): Added zcmp with version 1.0. (riscv_parse_check_conflicts): Zcmp conflicts with d/zcd. (riscv_multi_subset_supports): Handle zcmp. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * config/tc-riscv.c (regno_to_reg_list): New function, used to map register to reg_list number. (reglist_lookup): Called reglist_lookup_internal. Return false if reg_list number is zero, which is an invalid value. (reglist_lookup_internal): Parse register list, and return the last register by regno_to_reg_list. (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/march-help.l: Updated. * testsuite/gas/riscv/zcmp-push-pop-fail.d: New test. * testsuite/gas/riscv/zcmp-push-pop-fail.l: New test. * testsuite/gas/riscv/zcmp-push-pop-fail.s: New test. * testsuite/gas/riscv/zcmp-push-pop.d: New test. * testsuite/gas/riscv/zcmp-push-pop.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH/MASK_CM_PUSH): New macros for zcmp. (MATCH/MASK_CM_POP): Ditto. (MATCH/MASK_CM_POPRET): Ditto. (MATCH/MASK_CM_POPRETZ): Ditto. (DECLARE_INSN): New declarations for zcmp. * opcode/riscv.h (EXTRACT/ENCODE/VALID_ZCMP_SPIMM): Handle spimm operand for zcmp. (OP_MASK_REG_LIST): Handle operand for zcmp register list. (OP_SH_REG_LIST): Ditto. (ZCMP_SP_ALIGNMENT): New argument, used in riscv_get_sp_base. (X_S0, X_S1, X_S2, X_S10, X_S11): New register numbers. (enum riscv_insn_class): Added INSN_CLASS_ZCMP. (extern riscv_get_sp_base): Added. opcodes/ChangeLog: * riscv-dis.c (print_reg_list): New function, used to get zcmp reg_list field. (riscv_get_spimm): New function, used to get zcmp sp adjustment immediate. (print_insn_args): Handle new operands for zcmp. * riscv-opc.c (riscv_get_sp_base): New function, used by gas and objdump. Get sp base adjustment. (riscv_opcodes): Added zcmp instructions.
2024-04-07Support APX NFCui, Lili1-0/+2
For the case when NDD and NF are both 0 in evex-promoted format, we will fully support and test it in another patch. gas/ChangeLog: * NEWS: Support Intel APX NF. * config/tc-i386.c (enum i386_error): Add unsupported_nf. (struct _i386_insn): Add has_nf. (is_apx_evex_encoding): Ditto. (build_apx_evex_prefix): Encode the NF bit. (md_assemble): Handle unsupported_nf. (parse_insn): Handle Prefix_NF and report bad for illegal combination. (can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf. (match_template): Support D for APX_F insns and check NF support. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add apx nf tests. * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test. * testsuite/gas/i386/x86-64-apx-nf.d: Ditto. * testsuite/gas/i386/x86-64-apx-nf.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Add %NF to the instructions that support APX NF and add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table. * i386-dis-evex-reg.h: Ditto. * i386-dis.c (struct instr_info): Add nf. (struct dis386): Add "NF" for EVEX.NF. (get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case. (print_insn): Handle ins.vex.nf. (putop): Handle "%NF". * i386-opc.h (Prefix_NF): New. * i386-opc.tbl: Added new entries to support full APX NF instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Regenerated.
2024-04-03x86/APX: Remove KEYLOCKER and SHA promotions from EVEX MAP4Cui, Lili1-0/+2
APX spec removed KEYLOCKER and SHA promotions from EVEX MAP4. https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html gas/ChangeLog: * NEWS: Mention that remove KEYLOCKER and SHA promotions from EVEX * MAP4. * config/tc-i386.c (process_operands): Removed special handling of * KEYLOCKER and SHA. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: Removed KEYLOCKER * and SHA instructions. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Removed KEYLOCKER and SHA instructions. * i386-dis-evex.h: Ditto. * i386-opc.tbl: Ditto. * i386-dis.c (print_vector_reg): Removed special handling of KEYLOCKER * and SHA.
2024-03-28gas: sanitize FB- and dollar-label usesJan Beulich1-0/+4
I don't view it as sensible to be more lax when it comes to references to (uses of) such labels compared to their definition: The latter has been limited to decimal numerics, while the former permitted any radix. Beyond that leading zeroes on such labels aren't helpful either. Imo labels and their use sites would better match literally, to avoid confusion. As it turns out, one z80 testcase actually had such an odd use of labels where definition and use don't match in spelling. That testcase is being adjusted accordingly. While there also adjust a comment on a local variable in integer_constant().
2024-03-28RISC-V: Removed privileged spec 1.9.1 support in assembler.Nelson Chu1-0/+3
Removed since it's may have lots of conflicts with the newer extensions, but still keep linker recognizes it in case of linking old objects. gas/ * NEWS: Updated. * config/tc-riscv.c (riscv_set_default_priv_spec): Regard 1.9.1 as an unknown version. (md_show_usage): Removed privileged spec 1.9.1 information. * testsuite/gas/riscv/attribute-05.s: Updated since privileged spec 1.9.1 is unsupported. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-12.d: Likewise. * testsuite/gas/riscv/attribute-13.d: Likewise. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. * testsuite/gas/riscv/csr.s: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.d: Removed. * testsuite/gas/riscv/csr-version-1p9p1.l: Removed. include/ * opcode/riscv-opc.h: Updated since privileged spec 1.9.1 is unsupported. ld/ * testsuite/ld-riscv-elf/attr-merge-priv-spec-01.d: Updated since privileged spec 1.9.1 is unsupported. * testsuite/ld-riscv-elf/attr-merge-priv-spec-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Likewise.
2024-03-15gas/NEWS: Remove mention of AArch64 B16B16 extensionAndrew Carlotti1-3/+0
This aligns the 2.42 NEWS with the update backported to the 2.42 release branch.
2024-03-01s390: Allow to explicitly omit base register operand in assemblyJens Remus1-0/+4
The base register operand B may be omitted in D(B) by coding D and in D(L,B) by coding D(L). The index register operand X may be omitted in D(X,B) by coding D(B) or explicitly omitted by coding D(,B). In both cases the omitted base register operand value defaults to zero. Allow to explicitly omit the base register operand B in D(X,B) and D(L,B) by coding D(X,) and D(L,). Default the omitted base register operand value to zero. gas/ * config/tc-s390.c: Allow to explicitly omit the base register operand in assembly. * NEWS: Mention that the base register now may be omitted on s390. * gas/testsuite/gas/s390/zarch-base-index-0.s: Update test cases for change to allow to explicitly omit the base register operand in assembly. * gas/testsuite/gas/s390/zarch-base-index-0.d: Likewise. * gas/testsuite/gas/s390/zarch-base-index-0-err.s: Likewise. * gas/testsuite/gas/s390/zarch-base-index-0-err.l: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index.s: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index.d: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index-err.s: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Warn when register name type does not match operandJens Remus1-0/+6
Print a warning message when the register type of a specified register name does not match with the operand's register type: operand {#}: expected {access|control|floating-point|general|vector} register name [as {base|index} register] Introduce a s390-specific assembler option "warn-regtype-mismatch" with the values "strict", "relaxed", and "no" as well as an option "no-warn-regtype-mismatch" which control whether the assembler performs register name type checks and generates above warning messages. warn-regtype-mismatch=strict: Perform strict register name type checks. warn-regtype-mismatch=relaxed: Perform relaxed register name type checks, which allow floating-point register (FPR) names %f0 to %f15 to be specified as argument to vector register (VR) operands and vector register (VR) names %v0 to %v15 to be specified as argument to floating-point register (FPR) operands. This is acceptable as the FPRs are embedded into the lower halves of the VRs. Make "relaxed" the default, as GCC generates assembler code using FPR and VR interchangeably, which would cause assembler warnings to be generated with "strict". warn-regtype-mismatch=no: no-warn-regtype-mismatch: Disable any register name type checks. Tag .insn pseudo mnemonics as such, to skip register name type checks on those. They need to be skipped, as there do not exist .insn pseudo mnemonics for every possible operand register type combination. Keep track of the currently parsed operand number to provide it as reference in warning messages. To verify that the introduction of this change does not unnecessarily affect the compilation of existing code the GNU Binutils, GNU C Library, and Linux Kernel have been build with the new assembler, verifying that the assembler did not generate any of the new warning messages. gas/ * config/tc-s390.c: Handle new assembler options "[no]warn-regtype-mismatch[=strict|relaxed|no". Annotate parsed register expressions with register type. Keep track of operand number being parsed. Print warning message in case of register type mismatch between instruction operand and parsed register expression. * doc/as.texi: Document new s390-specific assembler options "[no-]warn-regtype-mismatch[=strict|relaxed|no]". * NEWS: Mention new s390-specific register name type checks and related assembler option "warn-regtype-mismatch=strict| relaxed|no". * testsuite/gas/s390/s390.exp: Add test cases for new assembler option "warn-regtype-mismatch={strict|relaxed}". * testsuite/gas/s390/esa-g5.s: Fix register types in tests for didbr, diebr, tbdr, and tbedr. * testsuite/gas/s390/zarch-z13.s: Fix register types in tests for vgef, vgeg, vscef, and vsceg. * testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.s: Tests for assembler option "warn-regtype-mismatch=strict". * testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.l: Likewise. * gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.s: Tests for assembler option "warn-regtype-mismatch=relaxed". * gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.l: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index-err.s: Update test cases for assembler option "warn-regtype-mismatch" defaulting to "relaxed". * testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. include/ * opcode/s390.h (S390_INSTR_FLAG_PSEUDO_MNEMONIC): Add instruction flag to tag .insn pseudo-mnemonics. opcodes/ * s390-opc.c (s390_opformats): Tag .insn pseudo-mnemonics as such. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01gas/NEWS: drop mention of Arm64's SVE2.1 and SME2.1Jan Beulich1-5/+1
... plus the SME part of B16B16. As per https://sourceware.org/pipermail/binutils/2024-February/132408.html SVE2.1 support is both incomplete and buggy. SME2.1 "support" goes as far as a single instruction (a subset of movaz forms) only. The SME part of B16B16 is entirely missing.
2024-02-19arm: Add support for Armv9.5-AClaudio Bantaloukas1-0/+2
2024-01-31Mention support for AMD/znver5 in GASNick Clifton1-0/+2
2024-01-25gas: Update NEWSAndrew Carlotti1-23/+37
Groups entries by architecture, and update AArch64 content.
2024-01-23[PATCH v2] gas/NEWS, ld/NEWS: Announce LoongArch changes in 2.42Xi Ruoyao1-0/+27
2024-01-15Add markers for 2.42 branchNick Clifton1-0/+3
2024-01-15aarch64: Add support for FEAT_SVE2p1.Srinath Parvathaneni1-0/+3
Hi, This patch add support for FEAT_SVE2p1 (SVE2.1 Extension) feature along with +sve2p1 optional flag to enabe this feature. Also support for following SVE2p1 instructions is added addqv, andqv, smaxqv, sminqv, umaxqv, uminqv and uminqv. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
2024-01-15aarch64: Add support for FEAT_SME2p1 instructions.Srinath Parvathaneni1-0/+3
Hi, This patch add support for FEAT_SME2p1 and "movaz" instructions along with the optional flag +sme2p1. Following "movaz" instructions are add: Move and zero two ZA tile slices to vector registers. Move and zero four ZA tile slices to vector registers. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
2024-01-15gas/NEWS: announce the new SCFI command line optionIndu Bhagat1-0/+3
2024-01-08arm: Add support for Armv8.9-A and Armv9.4-Asrinath1-0/+2
This patch adds AArch32 support for -march=armv8.9-a and -march=armv9.4-a. The behaviour of the new options can be expressed using a combination of existing feature flags and tables. The cpu_arch_ver entries for ARM_ARCH_V9_4A and ARM_ARCH_V8_9A are technically redundant but it including them for macro code consistency across architectures.
2024-01-04Update year range in copyright notice of binutils filesAlan Modra1-1/+1
Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out */po/*.pot which we don't update frequently.
2023-12-28gas: Mention initial support for Intel APX in NEWSH.J. Lu1-0/+2
2023-12-15aarch64: Enable Cortex-X3 CPUMatthieu Longo1-0/+2
Hi, This patch adds support for the Cortex-X3 CPU to binutils. Gas regression testing for aarch64-none-linux-gnu target and found no regressions. Ok for binutils-master? I don't have commit access so I need someone to commit on my behalf. Regards, Matthieu.
generated by cgit v1.1 at 2024-10-10 12:11:25 +0000