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AgeCommit message (Expand)AuthorFilesLines
2017-12-01Update and clean up RISC-V gas documentation.Jim Wilson1-0/+11
2017-12-01Use consistent types for holding instructions, instruction masks, etc.Peter Bergner1-0/+12
2017-11-30x86: drop Vec_Disp8Jan Beulich1-0/+12
2017-11-30x86/Intel: issue diagnostics for redundant segment override prefixesJan Beulich1-0/+12
2017-11-30Revert "x86: Update segment register check in Intel syntax"Jan Beulich1-13/+0
2017-11-29Give Palmer co-credit for last patch.Jim Wilson1-0/+1
2017-11-29Fix riscv malloc error on small alignment after norvc.Jim Wilson1-0/+7
2017-11-29In x86 -n docs, mention that you need an explicit nop fill byte.Jim Wilson1-0/+5
2017-11-29[GAS][AARCH64]Fix a typo for IP1 register alias.Renlin Li1-0/+6
2017-11-29Support --localedir, --datarootdir and --datadirStefan Stroe1-0/+6
2017-11-29Use the record_alignment function when creating a .note section, in case the ...Nick Clifton1-1/+6
2017-11-27Compress loads/stores with implicit 0 offset.Jim Wilson1-0/+13
2017-11-27gas: xtensa: speed up find_trampoline_segMax Filippov1-0/+5
2017-11-27gas: xtensa: implement trampoline coalescingMax Filippov1-0/+29
2017-11-27gas: xtensa: reuse trampoline placement codeMax Filippov1-0/+11
2017-11-27gas: xtensa: rewrite xg_relax_trampolineMax Filippov1-0/+33
2017-11-27gas: xtensa: merge trampoline_frag into xtensa_frag_typeMax Filippov1-0/+22
2017-11-27gas: xtensa: reuse find_trampoline_segMax Filippov1-0/+7
2017-11-27gas: xtensa: extract jump assembling for trampolinesMax Filippov1-0/+7
2017-11-27gas: extract xg_relax_trampoline from xtensa_relax_fragMax Filippov1-0/+6
2017-11-27When creating a .note section to contain a version note, set the section alig...Nick Clifton1-0/+6
2017-11-26gas: Update x86 sse-noavx testsH.J. Lu1-0/+9
2017-11-24Add reference to implicit use in _bfd_elf_is_local_label_name.Jim Wilson1-0/+4
2017-11-24x86: reject further invalid AVX-512 masking constructsJan Beulich1-0/+11
2017-11-24x86: don't omit disambiguating suffixes from "fi*"Jan Beulich1-0/+9
2017-11-23Fix vax/ns32k/mmix gas testsuite regression.Jim Wilson1-0/+3
2017-11-23Fix build error with --enable-targets=all.Jim Wilson1-0/+6
2017-11-23Add Disp8MemShift for AVX512 VAES instructions.Igor Tsimbalist1-0/+23
2017-11-23x86: fix AVX-512 16-bit addressingJan Beulich1-0/+7
2017-11-23x86-64: always use unsigned 32-bit reloc for 32-bit addressing w/o base regJan Beulich1-0/+9
2017-11-23x86: drop redundant VSIB handling codeJan Beulich1-0/+5
2017-11-23x86: correct UDnJan Beulich1-0/+9
2017-11-23x86/Intel: don't report multiple errors for a single insn operandJan Beulich1-0/+7
2017-11-22Riscv ld-elf/stab failure and fake label cleanup.Jim Wilson1-0/+21
2017-11-22Update docs on filling text with nops.Jim Wilson1-0/+5
2017-11-22[GAS/ARM] Clarify relation between reg_expected_msgs and arm_reg_typeThomas Preud'homme1-0/+7
2017-11-22[ARC] Fix handling of ARCv2 H-register class.claziss1-0/+4
2017-11-21x86: Add tests for -n option of x86 assemblerH.J. Lu1-0/+8
2017-11-21[ARC] Improve printing of pc-relative instructions.claziss1-0/+25
2017-11-21xtensa error messageAlan Modra1-0/+5
2017-11-21mingw gas testsuite fixAlan Modra1-0/+4
2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina1-0/+7
2017-11-16Correct AArch64 crypto dependencies.Tamar Christina1-0/+7
2017-11-16Update documentation for Arvm8.4-A changes to AArch64.Tamar Christina1-0/+5
2017-11-16Add assembler and disassembler support for the new Armv8.4-a instructions for...Tamar Christina1-0/+15
2017-11-16x86: ignore high register select bit(s) in 32- and 16-bit modesJan Beulich1-0/+6
2017-11-16ix86/Intel: don't require memory operand size specifier for PTWRITEJan Beulich1-0/+9
2017-11-16i386: Replace .code64/.code32 with .byteH.J. Lu1-0/+5
2017-11-15Separate the new FP16 instructions backported from Armv8.4-a to Armv8.2-a int...Tamar Christina1-0/+10
2017-11-15Add support to readelf and objdump for following links to separate debug info...Nick Clifton1-0/+17
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