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AgeCommit message (Expand)AuthorFilesLines
2018-07-02microMIPS/GAS: Handle several percent-ops with macrosMaciej W. Rozycki1-0/+20
2018-07-02microMIPS/BFD: Add missing NewABI TLS and miscellaneous relocationsMaciej W. Rozycki1-0/+6
2018-07-02[ARM] Update bfd's Tag_CPU_arch knowledgeThomas Preud'homme1-0/+5
2018-07-02Fix use of "command line X" in binutils docThomas Preud'homme1-0/+36
2018-06-29RISC-V: Add gas support for "fp" register.Jim Wilson1-0/+4
2018-06-29[Patch AArch64] Warn on unpredictable stlxrb , stlxrh and stlxr cases.Ramana Radhakrishnan1-0/+7
2018-06-29Fix AArch64 encodings for by element instructions.Tamar Christina1-0/+12
2018-06-27gas object file locationsAlan Modra1-0/+7
2018-06-26Updated translations.Nick Clifton1-0/+4
2018-06-26Fix the MSP430 assembler's parsing of register names.Nick Clifton1-0/+7
2018-06-24Regenerate configure and pot files with updated binutils version number.Nick Clifton1-0/+5
2018-06-24Add 2.30 branch notes to ChangeLogs and NEWS files.Nick Clifton1-0/+5
2018-06-22Correct negs aliasing on AArch64.Tamar Christina1-0/+5
2018-06-21Regen doc/Makefile.inAlan Modra1-0/+5
2018-06-20Change the ARM assembler's ADR and ADRl pseudo-ops so that they will only set...Nick Clifton1-0/+14
2018-06-20RISC-V: Accept constant operands in la and llaSebastian Huber1-0/+13
2018-06-19Bump to autoconf 2.69 and automake 1.15.1Simon Marchi1-0/+18
2018-06-14MIPS: Add Global INValidate ASE supportFaraz Shahbazker1-0/+23
2018-06-14MIPS: Add CRC ASE support (ChangeLog)Maciej W. Rozycki1-0/+1
2018-06-13MIPS: Add CRC ASE supportScott Egerton1-0/+29
2018-06-11MIPS/GAS: Correct `-O0' and `-O' option help, add `-O1' and `-O2'Maciej W. Rozycki1-0/+5
2018-06-08[arm][gas] Add support for Arm Cortex-A76kyrtka011-0/+5
2018-06-08[AArch64][gas] Add support for Arm Cortex-A76kyrtka011-0/+5
2018-06-08Prevent undefined FMOV instructions being accepted by the AArch64 assembler.Egeyar Bagcioglu1-0/+11
2018-06-07Fix AArch64 unintialized variable which can cause diagnostic failures.Tamar Christina1-0/+6
2018-06-06Update the AArch64 assembler to note that the Qualcomm Saphira cpu supports A...Sameera Deshpande1-0/+5
2018-06-05Another s12z regenAlan Modra1-0/+4
2018-06-04xtensa: add separate property sections optionMax Filippov1-0/+11
2018-06-01Bump version number to 2.30.52H.J. Lu1-0/+4
2018-06-01Drop view when consuming line infoAlexandre Oliva1-0/+4
2018-06-01x86: don't emit REX.W for SLDT and STRJan Beulich1-0/+5
2018-06-01x86: relax redundant REX prefix checkJan Beulich1-0/+8
2018-06-01x86: simplify control register checkJan Beulich1-0/+5
2018-06-01x86: tighten condition for emitting LOCK on control register accessesJan Beulich1-0/+6
2018-06-01x86/Intel: accept "oword ptr" for INVPCIDJan Beulich1-0/+10
2018-05-30Add znver2 support.Amit Pawar1-0/+14
2018-05-25s12z regenAlan Modra1-0/+4
2018-05-24RISC-V: Fix .align handling when .option norelax.Jim Wilson1-0/+12
2018-05-21Remove fake operand handling for extended mnemonics.Peter Bergner1-0/+9
2018-05-18RISC-V: Add RV32E support.Jim Wilson1-0/+15
2018-05-18Add support for the Freescale s12z processor.John Darrington1-0/+216
2018-05-16NDS32/GAS: Correct an `expr' global shadowing error for pre-4.8 GCCMaciej W. Rozycki1-0/+5
2018-05-15Implement Read/Write constraints on system registers on AArch64Tamar Christina1-0/+10
2018-05-15Allow non-fatal errors to be emitted and for disassembly notes be placed on A...Tamar Christina1-0/+8
2018-05-15Modify AArch64 Assembly and disassembly functions to be able to fail and repo...Tamar Christina1-0/+6
2018-05-14Stop generating GNU build notes for linkonce sections.Nick Clifton1-0/+5
2018-05-14Fix a problem in the assembler when checking for overlapping input and output...Nick Clifton1-0/+6
2018-05-12score gcc-8 warning fixesAlan Modra1-0/+6
2018-05-10Allow integer immediates for AArch64 fmov instructions.Tamar Christina1-0/+10
2018-05-10Allow integer immediate for VFP vmov instructions.Tamar Christina1-0/+7
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