diff options
Diffstat (limited to 'gas')
23 files changed, 335 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 39884ef..b80cec5 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2014-02-12 Ilya Tocar <ilya.tocar@intel.com> + + * config/tc-i386.c (cpu_arch): Add .clflushopt, .xsavec, .xsaves. + * doc/c-i386.texi: Document .xsavec/xsavec/.xsaves/xsaves/ + clflushopt/.clfushopt. + 2014-02-10 Alan Modra <amodra@gmail.com> * po/POTFILES.in: Regenerate. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 7f35f05..49626cd 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -904,6 +904,12 @@ static const arch_entry cpu_arch[] = CPU_MPX_FLAGS, 0, 0 }, { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, CPU_SHA_FLAGS, 0, 0 }, + { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, + CPU_CLFLUSHOPT_FLAGS, 0, 0 }, + { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, + CPU_XSAVEC_FLAGS, 0, 0 }, + { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, + CPU_XSAVES_FLAGS, 0, 0 }, }; #ifdef I386COFF diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 8a4a5f1..0fa8df1 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -1063,6 +1063,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw} @item @samp{.smap} @tab @samp{.mpx} @item @samp{.smap} @tab @samp{.sha} +@item @samp{.smap} @tab @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm} @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16} diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 4941ba3..4555408 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,25 @@ +2014-02-12 Ilya Tocar <ilya.tocar@intel.com> + + * gas/i386/clflushopt-intel.d: New. + * gas/i386/clflushopt.d: Ditto. + * gas/i386/clflushopt.s: Ditto. + * gas/i386/i386.exp: Run new tests. + * gas/i386/x86-64-clflushopt-intel.d: New. + * gas/i386/x86-64-clflushopt.d: Ditto. + * gas/i386/x86-64-clflushopt.s: Ditto. + * gas/i386/x86-64-xsavec-intel.d: Ditto. + * gas/i386/x86-64-xsavec.d: Ditto. + * gas/i386/x86-64-xsavec.s: Ditto. + * gas/i386/x86-64-xsaves-intel.d: Ditto. + * gas/i386/x86-64-xsaves.d: Ditto. + * gas/i386/x86-64-xsaves.s: Ditto. + * gas/i386/xsavec-intel.d: Ditto. + * gas/i386/xsavec.d: Ditto. + * gas/i386/xsavec.s: Ditto. + * gas/i386/xsaves-intel.d: Ditto. + * gas/i386/xsaves.d: Ditto. + * gas/i386/xsaves.s: Ditto. + 2014-01-31 Michael Zolotukhin <michael.v.zolotukhin@gmail.com> PR gas/16488 diff --git a/gas/testsuite/gas/i386/clflushopt-intel.d b/gas/testsuite/gas/i386/clflushopt-intel.d new file mode 100644 index 0000000..b062e18 --- /dev/null +++ b/gas/testsuite/gas/i386/clflushopt-intel.d @@ -0,0 +1,16 @@ +#as: +#objdump: -dw -Mintel +#name: i386 CLFLUSHOPT insns (Intel disassembly) +#source: clflushopt.s + +.*: +file format .* + + +Disassembly of section \.text: + +00000000 <_start>: +[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt BYTE PTR \[ecx\] +[ ]*[a-f0-9]+:[ ]*66 0f ae bc f4 c0 1d fe ff[ ]*clflushopt BYTE PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt BYTE PTR \[ecx\] +[ ]*[a-f0-9]+:[ ]*66 0f ae bc f4 c0 1d fe ff[ ]*clflushopt BYTE PTR \[esp\+esi\*8-0x1e240\] +#pass diff --git a/gas/testsuite/gas/i386/clflushopt.d b/gas/testsuite/gas/i386/clflushopt.d new file mode 100644 index 0000000..115f5ed --- /dev/null +++ b/gas/testsuite/gas/i386/clflushopt.d @@ -0,0 +1,16 @@ +#as: +#objdump: -dw +#name: i386 CLFLUSHOPT insns +#source: clflushopt.s + +.*: +file format .* + + +Disassembly of section \.text: + +00000000 <_start>: +[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt \(%ecx\) +[ ]*[a-f0-9]+:[ ]*66 0f ae bc f4 c0 1d fe ff[ ]*clflushopt -0x1e240\(%esp,%esi,8\) +[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt \(%ecx\) +[ ]*[a-f0-9]+:[ ]*66 0f ae bc f4 c0 1d fe ff[ ]*clflushopt -0x1e240\(%esp,%esi,8\) +#pass diff --git a/gas/testsuite/gas/i386/clflushopt.s b/gas/testsuite/gas/i386/clflushopt.s new file mode 100644 index 0000000..a6d4990 --- /dev/null +++ b/gas/testsuite/gas/i386/clflushopt.s @@ -0,0 +1,12 @@ +# Check 32bit CLFLUSHOPT instructions + + .allow_index_reg + .text +_start: + + clflushopt (%ecx) # CLFLUSHOPT + clflushopt -123456(%esp,%esi,8) # CLFLUSHOPT + + .intel_syntax noprefix + clflushopt BYTE PTR [ecx] # CLFLUSHOPT + clflushopt BYTE PTR [esp+esi*8-123456] # CLFLUSHOPT diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index b70f01c..8132d0d 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -269,6 +269,12 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_list_test "mpx-inval-1" "-al" run_dump_test "mpx-add-bnd-prefix" run_dump_test "sha" + run_dump_test "clflushopt" + run_dump_test "clflushopt-intel" + run_dump_test "xsavec" + run_dump_test "xsavec-intel" + run_dump_test "xsaves" + run_dump_test "xsaves-intel" run_dump_test "disassem" # These tests require support for 8 and 16 bit relocs, @@ -559,6 +565,12 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_dump_test "x86-64-mpx-addr32" run_dump_test "x86-64-mpx-add-bnd-prefix" run_dump_test "x86-64-sha" + run_dump_test "x86-64-clflushopt" + run_dump_test "x86-64-clflushopt-intel" + run_dump_test "x86-64-xsavec" + run_dump_test "x86-64-xsavec-intel" + run_dump_test "x86-64-xsaves" + run_dump_test "x86-64-xsaves-intel" if { ![istarget "*-*-aix*"] && ![istarget "*-*-beos*"] diff --git a/gas/testsuite/gas/i386/x86-64-clflushopt-intel.d b/gas/testsuite/gas/i386/x86-64-clflushopt-intel.d new file mode 100644 index 0000000..6ab5e2c --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-clflushopt-intel.d @@ -0,0 +1,16 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 CLFLUSHOPT insns (Intel disassembly) +#source: x86-64-clflushopt.s + +.*: +file format .* + + +Disassembly of section \.text: + +0+ <_start>: +[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt BYTE PTR \[rcx\] +[ ]*[a-f0-9]+:[ ]*66 42 0f ae bc f0 23 01 00 00[ ]*clflushopt BYTE PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt BYTE PTR \[rcx\] +[ ]*[a-f0-9]+:[ ]*66 42 0f ae bc f0 34 12 00 00[ ]*clflushopt BYTE PTR \[rax\+r14\*8\+0x1234\] +#pass diff --git a/gas/testsuite/gas/i386/x86-64-clflushopt.d b/gas/testsuite/gas/i386/x86-64-clflushopt.d new file mode 100644 index 0000000..3c400a8 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-clflushopt.d @@ -0,0 +1,16 @@ +#as: +#objdump: -dw +#name: x86_64 CLFLUSHOPT insns +#source: x86-64-clflushopt.s + +.*: +file format .* + + +Disassembly of section \.text: + +0+ <_start>: +[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt \(%rcx\) +[ ]*[a-f0-9]+:[ ]*66 42 0f ae bc f0 23 01 00 00[ ]*clflushopt 0x123\(%rax,%r14,8\) +[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt \(%rcx\) +[ ]*[a-f0-9]+:[ ]*66 42 0f ae bc f0 34 12 00 00[ ]*clflushopt 0x1234\(%rax,%r14,8\) +#pass diff --git a/gas/testsuite/gas/i386/x86-64-clflushopt.s b/gas/testsuite/gas/i386/x86-64-clflushopt.s new file mode 100644 index 0000000..3e64d06 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-clflushopt.s @@ -0,0 +1,12 @@ +# Check 64bit CLFLUSHOPT instructions + + .allow_index_reg + .text +_start: + + clflushopt (%rcx) # CLFLUSHOPT + clflushopt 0x123(%rax,%r14,8) # CLFLUSHOPT + + .intel_syntax noprefix + clflushopt BYTE PTR [rcx] # CLFLUSHOPT + clflushopt BYTE PTR [rax+r14*8+0x1234] # CLFLUSHOPT diff --git a/gas/testsuite/gas/i386/x86-64-xsavec-intel.d b/gas/testsuite/gas/i386/x86-64-xsavec-intel.d new file mode 100644 index 0000000..cb5214d --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-xsavec-intel.d @@ -0,0 +1,16 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 XSAVEC insns (Intel disassembly) +#source: x86-64-xsavec.s + +.*: +file format .* + + +Disassembly of section \.text: + +0+ <_start>: +[ ]*[a-f0-9]+:[ ]*48 0f c7 21[ ]*xsavec64 \[rcx\] +[ ]*[a-f0-9]+:[ ]*4a 0f c7 a4 f0 23 01 00 00[ ]*xsavec64 \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*48 0f c7 21[ ]*xsavec64 \[rcx\] +[ ]*[a-f0-9]+:[ ]*4a 0f c7 a4 f0 34 12 00 00[ ]*xsavec64 \[rax\+r14\*8\+0x1234\] +#pass diff --git a/gas/testsuite/gas/i386/x86-64-xsavec.d b/gas/testsuite/gas/i386/x86-64-xsavec.d new file mode 100644 index 0000000..939aef8 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-xsavec.d @@ -0,0 +1,16 @@ +#as: +#objdump: -dw +#name: x86_64 XSAVEC insns +#source: x86-64-xsavec.s + +.*: +file format .* + + +Disassembly of section \.text: + +0+ <_start>: +[ ]*[a-f0-9]+:[ ]*48 0f c7 21[ ]*xsavec64 \(%rcx\) +[ ]*[a-f0-9]+:[ ]*4a 0f c7 a4 f0 23 01 00 00[ ]*xsavec64 0x123\(%rax,%r14,8\) +[ ]*[a-f0-9]+:[ ]*48 0f c7 21[ ]*xsavec64 \(%rcx\) +[ ]*[a-f0-9]+:[ ]*4a 0f c7 a4 f0 34 12 00 00[ ]*xsavec64 0x1234\(%rax,%r14,8\) +#pass diff --git a/gas/testsuite/gas/i386/x86-64-xsavec.s b/gas/testsuite/gas/i386/x86-64-xsavec.s new file mode 100644 index 0000000..7d446d0 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-xsavec.s @@ -0,0 +1,12 @@ +# Check 64bit XSAVEC instructions + + .allow_index_reg + .text +_start: + + xsavec64 (%rcx) # XSAVEC + xsavec64 0x123(%rax,%r14,8) # XSAVEC + + .intel_syntax noprefix + xsavec64 [rcx] # XSAVEC + xsavec64 [rax+r14*8+0x1234] # XSAVEC diff --git a/gas/testsuite/gas/i386/x86-64-xsaves-intel.d b/gas/testsuite/gas/i386/x86-64-xsaves-intel.d new file mode 100644 index 0000000..dde379c --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-xsaves-intel.d @@ -0,0 +1,20 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 XSAVES insns (Intel disassembly) +#source: x86-64-xsaves.s + +.*: +file format .* + + +Disassembly of section \.text: + +0+ <_start>: +[ ]*[a-f0-9]+:[ ]*48 0f c7 29[ ]*xsaves64 \[rcx\] +[ ]*[a-f0-9]+:[ ]*4a 0f c7 ac f0 23 01 00 00[ ]*xsaves64 \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*48 0f c7 19[ ]*xrstors64 \[rcx\] +[ ]*[a-f0-9]+:[ ]*4a 0f c7 9c f0 23 01 00 00[ ]*xrstors64 \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*48 0f c7 29[ ]*xsaves64 \[rcx\] +[ ]*[a-f0-9]+:[ ]*4a 0f c7 ac f0 34 12 00 00[ ]*xsaves64 \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*48 0f c7 19[ ]*xrstors64 \[rcx\] +[ ]*[a-f0-9]+:[ ]*4a 0f c7 9c f0 34 12 00 00[ ]*xrstors64 \[rax\+r14\*8\+0x1234\] +#pass diff --git a/gas/testsuite/gas/i386/x86-64-xsaves.d b/gas/testsuite/gas/i386/x86-64-xsaves.d new file mode 100644 index 0000000..e715529 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-xsaves.d @@ -0,0 +1,20 @@ +#as: +#objdump: -dw +#name: x86_64 XSAVES insns +#source: x86-64-xsaves.s + +.*: +file format .* + + +Disassembly of section \.text: + +0+ <_start>: +[ ]*[a-f0-9]+:[ ]*48 0f c7 29[ ]*xsaves64 \(%rcx\) +[ ]*[a-f0-9]+:[ ]*4a 0f c7 ac f0 23 01 00 00[ ]*xsaves64 0x123\(%rax,%r14,8\) +[ ]*[a-f0-9]+:[ ]*48 0f c7 19[ ]*xrstors64 \(%rcx\) +[ ]*[a-f0-9]+:[ ]*4a 0f c7 9c f0 23 01 00 00[ ]*xrstors64 0x123\(%rax,%r14,8\) +[ ]*[a-f0-9]+:[ ]*48 0f c7 29[ ]*xsaves64 \(%rcx\) +[ ]*[a-f0-9]+:[ ]*4a 0f c7 ac f0 34 12 00 00[ ]*xsaves64 0x1234\(%rax,%r14,8\) +[ ]*[a-f0-9]+:[ ]*48 0f c7 19[ ]*xrstors64 \(%rcx\) +[ ]*[a-f0-9]+:[ ]*4a 0f c7 9c f0 34 12 00 00[ ]*xrstors64 0x1234\(%rax,%r14,8\) +#pass diff --git a/gas/testsuite/gas/i386/x86-64-xsaves.s b/gas/testsuite/gas/i386/x86-64-xsaves.s new file mode 100644 index 0000000..f65b51c --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-xsaves.s @@ -0,0 +1,16 @@ +# Check 64bit XSAVES instructions + + .allow_index_reg + .text +_start: + + xsaves64 (%rcx) # XSAVES + xsaves64 0x123(%rax,%r14,8) # XSAVES + xrstors64 (%rcx) # XSAVES + xrstors64 0x123(%rax,%r14,8) # XSAVES + + .intel_syntax noprefix + xsaves64 [rcx] # XSAVES + xsaves64 [rax+r14*8+0x1234] # XSAVES + xrstors64 [rcx] # XSAVES + xrstors64 [rax+r14*8+0x1234] # XSAVES diff --git a/gas/testsuite/gas/i386/xsavec-intel.d b/gas/testsuite/gas/i386/xsavec-intel.d new file mode 100644 index 0000000..3751f10 --- /dev/null +++ b/gas/testsuite/gas/i386/xsavec-intel.d @@ -0,0 +1,16 @@ +#as: +#objdump: -dw -Mintel +#name: i386 XSAVEC insns (Intel disassembly) +#source: xsavec.s + +.*: +file format .* + + +Disassembly of section \.text: + +00000000 <_start>: +[ ]*[a-f0-9]+:[ ]*0f c7 21[ ]*xsavec \[ecx\] +[ ]*[a-f0-9]+:[ ]*0f c7 a4 f4 c0 1d fe ff[ ]*xsavec \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*0f c7 21[ ]*xsavec \[ecx\] +[ ]*[a-f0-9]+:[ ]*0f c7 a4 f4 c0 1d fe ff[ ]*xsavec \[esp\+esi\*8-0x1e240\] +#pass diff --git a/gas/testsuite/gas/i386/xsavec.d b/gas/testsuite/gas/i386/xsavec.d new file mode 100644 index 0000000..b0d9ee1 --- /dev/null +++ b/gas/testsuite/gas/i386/xsavec.d @@ -0,0 +1,16 @@ +#as: +#objdump: -dw +#name: i386 XSAVEC insns +#source: xsavec.s + +.*: +file format .* + + +Disassembly of section \.text: + +00000000 <_start>: +[ ]*[a-f0-9]+:[ ]*0f c7 21[ ]*xsavec \(%ecx\) +[ ]*[a-f0-9]+:[ ]*0f c7 a4 f4 c0 1d fe ff[ ]*xsavec -0x1e240\(%esp,%esi,8\) +[ ]*[a-f0-9]+:[ ]*0f c7 21[ ]*xsavec \(%ecx\) +[ ]*[a-f0-9]+:[ ]*0f c7 a4 f4 c0 1d fe ff[ ]*xsavec -0x1e240\(%esp,%esi,8\) +#pass diff --git a/gas/testsuite/gas/i386/xsavec.s b/gas/testsuite/gas/i386/xsavec.s new file mode 100644 index 0000000..93415d8 --- /dev/null +++ b/gas/testsuite/gas/i386/xsavec.s @@ -0,0 +1,12 @@ +# Check 32bit XSAVEC instructions + + .allow_index_reg + .text +_start: + + xsavec (%ecx) # XSAVEC + xsavec -123456(%esp,%esi,8) # XSAVEC + + .intel_syntax noprefix + xsavec [ecx] # XSAVEC + xsavec [esp+esi*8-123456] # XSAVEC diff --git a/gas/testsuite/gas/i386/xsaves-intel.d b/gas/testsuite/gas/i386/xsaves-intel.d new file mode 100644 index 0000000..edb3d57 --- /dev/null +++ b/gas/testsuite/gas/i386/xsaves-intel.d @@ -0,0 +1,20 @@ +#as: +#objdump: -dw -Mintel +#name: i386 XSAVES insns (Intel disassembly) +#source: xsaves.s + +.*: +file format .* + + +Disassembly of section \.text: + +00000000 <_start>: +[ ]*[a-f0-9]+:[ ]*0f c7 29[ ]*xsaves \[ecx\] +[ ]*[a-f0-9]+:[ ]*0f c7 ac f4 c0 1d fe ff[ ]*xsaves \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*0f c7 19[ ]*xrstors \[ecx\] +[ ]*[a-f0-9]+:[ ]*0f c7 9c f4 c0 1d fe ff[ ]*xrstors \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*0f c7 29[ ]*xsaves \[ecx\] +[ ]*[a-f0-9]+:[ ]*0f c7 ac f4 c0 1d fe ff[ ]*xsaves \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*0f c7 19[ ]*xrstors \[ecx\] +[ ]*[a-f0-9]+:[ ]*0f c7 9c f4 c0 1d fe ff[ ]*xrstors \[esp\+esi\*8-0x1e240\] +#pass diff --git a/gas/testsuite/gas/i386/xsaves.d b/gas/testsuite/gas/i386/xsaves.d new file mode 100644 index 0000000..6984b79 --- /dev/null +++ b/gas/testsuite/gas/i386/xsaves.d @@ -0,0 +1,20 @@ +#as: +#objdump: -dw +#name: i386 XSAVES insns +#source: xsaves.s + +.*: +file format .* + + +Disassembly of section \.text: + +00000000 <_start>: +[ ]*[a-f0-9]+:[ ]*0f c7 29[ ]*xsaves \(%ecx\) +[ ]*[a-f0-9]+:[ ]*0f c7 ac f4 c0 1d fe ff[ ]*xsaves -0x1e240\(%esp,%esi,8\) +[ ]*[a-f0-9]+:[ ]*0f c7 19[ ]*xrstors \(%ecx\) +[ ]*[a-f0-9]+:[ ]*0f c7 9c f4 c0 1d fe ff[ ]*xrstors -0x1e240\(%esp,%esi,8\) +[ ]*[a-f0-9]+:[ ]*0f c7 29[ ]*xsaves \(%ecx\) +[ ]*[a-f0-9]+:[ ]*0f c7 ac f4 c0 1d fe ff[ ]*xsaves -0x1e240\(%esp,%esi,8\) +[ ]*[a-f0-9]+:[ ]*0f c7 19[ ]*xrstors \(%ecx\) +[ ]*[a-f0-9]+:[ ]*0f c7 9c f4 c0 1d fe ff[ ]*xrstors -0x1e240\(%esp,%esi,8\) +#pass diff --git a/gas/testsuite/gas/i386/xsaves.s b/gas/testsuite/gas/i386/xsaves.s new file mode 100644 index 0000000..697b3dd --- /dev/null +++ b/gas/testsuite/gas/i386/xsaves.s @@ -0,0 +1,16 @@ +# Check 32bit XSAVES instructions + + .allow_index_reg + .text +_start: + + xsaves (%ecx) # XSAVES + xsaves -123456(%esp,%esi,8) # XSAVES + xrstors (%ecx) # XSAVES + xrstors -123456(%esp,%esi,8) # XSAVES + + .intel_syntax noprefix + xsaves [ecx] # XSAVES + xsaves [esp+esi*8-123456] # XSAVES + xrstors [ecx] # XSAVES + xrstors [esp+esi*8-123456] # XSAVES |