diff options
Diffstat (limited to 'gas')
-rw-r--r-- | gas/ChangeLog | 14 | ||||
-rw-r--r-- | gas/config/tc-riscv.c | 14 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/bitmanip-insns-32.d | 37 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/bitmanip-insns-64.d | 55 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/bitmanip-insns.s | 58 |
5 files changed, 177 insertions, 1 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index b0033ef..c99e1b3 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,17 @@ +2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com> + Jim Wilson <jimw@sifive.com> + Andrew Waterman <andrew@sifive.com> + Maxim Blinov <maxim.blinov@embecosm.com> + Kito Cheng <kito.cheng@sifive.com> + Nelson Chu <nelson.chu@sifive.com> + + * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZB*. + (riscv_get_default_ext_version): Do not check the default_isa_spec when + the version defined in the riscv_opcodes table is ISA_SPEC_CLASS_DRAFT. + * testsuite/gas/riscv/bitmanip-insns-32.d: New testcase. + * testsuite/gas/riscv/bitmanip-insns-64.d: Likewise. + * testsuite/gas/riscv/bitmanip-insns.s: Likewise. + 2021-01-06 Alan Modra <amodra@gmail.com> * testsuite/gas/sparc/sparc.exp: Move 64-bit tests inside gas_64_check. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 55d5f1b..052199e 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -251,6 +251,16 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class) case INSN_CLASS_ZIFENCEI: return riscv_subset_supports ("zifencei"); + case INSN_CLASS_ZBA: + return riscv_subset_supports ("zba"); + case INSN_CLASS_ZBB: + return riscv_subset_supports ("zbb"); + case INSN_CLASS_ZBC: + return riscv_subset_supports ("zbc"); + case INSN_CLASS_ZBA_OR_ZBB: + return (riscv_subset_supports ("zba") + || riscv_subset_supports ("zbb")); + default: as_fatal ("Unreachable"); return FALSE; @@ -296,7 +306,8 @@ riscv_get_default_ext_version (const char *name, && ext->name && strcmp (ext->name, name) == 0) { - if (ext->isa_spec_class == default_isa_spec) + if (ext->isa_spec_class == ISA_SPEC_CLASS_DRAFT + || ext->isa_spec_class == default_isa_spec) { *major_version = ext->major_version; *minor_version = ext->minor_version; @@ -1454,6 +1465,7 @@ riscv_ext (int destreg, int srcreg, unsigned shift, bfd_boolean sign) } /* Expand RISC-V assembly macros into one or more instructions. */ + static void macro (struct riscv_cl_insn *ip, expressionS *imm_expr, bfd_reloc_code_real_type *imm_reloc) diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-32.d b/gas/testsuite/gas/riscv/bitmanip-insns-32.d new file mode 100644 index 0000000..b218f96 --- /dev/null +++ b/gas/testsuite/gas/riscv/bitmanip-insns-32.d @@ -0,0 +1,37 @@ +#as: -march=rv32i_zba_zbb_zbc +#source: bitmanip-insns.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+0805c533[ ]+zext.h[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+6985d513[ ]+rev8[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+2875d513[ ]+orc.b[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+60059513[ ]+clz[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+60159513[ ]+ctz[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+60259513[ ]+cpop[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+60459513[ ]+sext.b[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+60559513[ ]+sext.h[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+00c5c533[ ]+xor[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+6005d513[ ]+rori[ ]+a0,a1,0x0 +[ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f +[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+6005d513[ ]+rori[ ]+a0,a1,0x0 +[ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f +[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2 diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-64.d b/gas/testsuite/gas/riscv/bitmanip-insns-64.d new file mode 100644 index 0000000..9914f3e --- /dev/null +++ b/gas/testsuite/gas/riscv/bitmanip-insns-64.d @@ -0,0 +1,55 @@ +#as: -march=rv64i_zba_zbb_zbc -defsym __64_bit__=1 +#source: bitmanip-insns.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+0805c53b[ ]+zext.h[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+6b85d513[ ]+rev8[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+2875d513[ ]+orc.b[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+0805853b[ ]+add.uw[ ]+a0,a1,zero +[ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+20c5a53b[ ]+sh1add.uw[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+20c5c53b[ ]+sh2add.uw[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+20c5e53b[ ]+sh3add.uw[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+08c5853b[ ]+add.uw[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0805951b[ ]+slli.uw[ ]+a0,a1,0x0 +[ ]+[0-9a-f]+:[ ]+0bf5951b[ ]+slli.uw[ ]+a0,a1,0x3f +[ ]+[0-9a-f]+:[ ]+60059513[ ]+clz[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+60159513[ ]+ctz[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+60259513[ ]+cpop[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+60459513[ ]+sext.b[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+60559513[ ]+sext.h[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+00c5c533[ ]+xor[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+6005d513[ ]+rori[ ]+a0,a1,0x0 +[ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f +[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+6005d513[ ]+rori[ ]+a0,a1,0x0 +[ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f +[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+6005951b[ ]+clzw[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+6015951b[ ]+ctzw[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+6025951b[ ]+cpopw[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+63f5d513[ ]+rori[ ]+a0,a1,0x3f +[ ]+[0-9a-f]+:[ ]+63f5d513[ ]+rori[ ]+a0,a1,0x3f +[ ]+[0-9a-f]+:[ ]+6005d51b[ ]+roriw[ ]+a0,a1,0x0 +[ ]+[0-9a-f]+:[ ]+61f5d51b[ ]+roriw[ ]+a0,a1,0x1f +[ ]+[0-9a-f]+:[ ]+60c5d53b[ ]+rorw[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+6005d51b[ ]+roriw[ ]+a0,a1,0x0 +[ ]+[0-9a-f]+:[ ]+61f5d51b[ ]+roriw[ ]+a0,a1,0x1f +[ ]+[0-9a-f]+:[ ]+60c5953b[ ]+rolw[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2 diff --git a/gas/testsuite/gas/riscv/bitmanip-insns.s b/gas/testsuite/gas/riscv/bitmanip-insns.s new file mode 100644 index 0000000..b14e89c --- /dev/null +++ b/gas/testsuite/gas/riscv/bitmanip-insns.s @@ -0,0 +1,58 @@ + # pseudo/aliaese + zext.h a0, a1 + rev8 a0, a1 + orc.b a0, a1 +.ifdef __64_bit__ + zext.w a0, a1 +.endif + + # ZBA + sh1add a0, a1, a2 + sh2add a0, a1, a2 + sh3add a0, a1, a2 +.ifdef __64_bit__ + sh1add.uw a0, a1, a2 + sh2add.uw a0, a1, a2 + sh3add.uw a0, a1, a2 + add.uw a0, a1, a2 + slli.uw a0, a1, 0 + slli.uw a0, a1, 63 +.endif + + # ZBB + clz a0, a1 + ctz a0, a1 + cpop a0, a1 + min a0, a1, a2 + max a0, a1, a2 + minu a0, a1, a2 + maxu a0, a1, a2 + sext.b a0, a1 + sext.h a0, a1 + andn a0, a1, a2 + orn a0, a1, a2 + xor a0, a1, a2 + rori a0, a1, 0 + rori a0, a1, 31 + ror a0, a1, a2 + ror a0, a1, 0 + ror a0, a1, 31 + rol a0, a1, a2 +.ifdef __64_bit__ + clzw a0, a1 + ctzw a0, a1 + cpopw a0, a1 + rori a0, a1, 63 + ror a0, a1, 63 + roriw a0, a1, 0 + roriw a0, a1, 31 + rorw a0, a1, a2 + rorw a0, a1, 0 + rorw a0, a1, 31 + rolw a0, a1, a2 +.endif + + # ZBC + clmul a0, a1, a2 + clmulh a0, a1, a2 + clmulr a0, a1, a2 |